KR970006304B1 - Time base corrector - Google Patents

Abstract

A time base corrector records video signal data for correcting the time base in a memory and reads the data from the memory according to a read clock and read reset signal to correct the time base of the video signal data. The time base corrector includes a read clock generator for generating the read clock according to the frequency of a reference color sub carrier, a second read reset signal generator for generating a first read reset signal which is obtained by dividing the read clock by a horizontal synchronous signal, a second read reset signal generator for generating a second read reset signal which is obtained by delaying the first read reset signal by half period of a color signal, and a read reset signal selector for outputting one of the first and second read reset signals according to a playback mode, thereby generating a read reset signal which controls reading data of the memory.

Description

Time base compensation device

1 is a block diagram of a conventional time-base correction device.

2 is a block diagram of a time axis correction device according to the present invention.

3 is a waveform diagram relating to FIG. 2;

4 is a diagram for explaining a frame and color signal phase of a video signal;

* Explanation of symbols for main parts of the drawings

21: analog-to-digital converter 22: memory

23: digital-analog converter 24: synchronization signal separator

25: light clock pulse generator 26: crystal oscillator

27: color correction device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal processing apparatus such as a laser disk player (LDP), and more particularly, to include a new correction circuit for correcting color signal phases different from normal playback during still / slow playback. A time axis correction apparatus of a video signal processing apparatus.

Time base correctors (hereinafter referred to as TBCs) include analog TBCs and digital TBCs. The former corrects the video signal in the form of an analog signal, and the latter converts the video signal into a digital signal once to correct it, and then restores the original analog signal. Therefore, the latter circuit configuration is considerably more complicated than the former, but has been widely used because of its many advantages with the development of IC technology.

1 is a block diagram of a conventional digital TBC.

The sync signal separator 14 separates the horizontal sync signal and the color burst from the reproduced video signal, and multiplies (or 4 times) the horizontal sync signal by a write clock pulse generator 15 to the light clock pulse. Occurs. The read clock pulse generator 16 generates the read clock pulses according to the frequency of the reference color subcarrier.

The video signal is converted into a digital signal by an analog-to-digital converter (ADC) 11 and written to the memory 12 in accordance with the light clock pulses. After a predetermined time, the data written in the memory 12 is read out according to the read clock pulse, converted into an analog signal by the D / A converter 23, and restored to the video signal through the low pass filter.

The timing at the time of recording the video signal data into the memory is an inequality interval because there is a variation in the time axis, but the time output variation is eliminated by storing a predetermined amount of data and reading it out with a clock pulse at an equal interval timing. Therefore, the lead clock pulses must occur accurately and consistently. The memory device is used in the form of a RAM or a shift register, and the memory capacity is about 1 line to 10 lines.

As shown in Fig. 4, the NTSC video signal has a different phase of the color signal during normal playback and still / slow playback. That is, in normal reproduction, the phase of the color signal is inverted at the frame period, but in still / slow reproduction, the phase of the color signal is not inverted because the same frame is repeatedly reproduced. Therefore, when still / slow playback undergoes the same time axis correction process as in normal playback, color signal phase is not reversed in the frame period, thereby causing a change in color.

Accordingly, an object of the present invention is to provide a time axis correction device including a color correction circuit for generating the same video signal as in normal playback by inverting the color signal phase at the frame period of the video signal during still / slow playback in a video signal processing apparatus. have.

In order to achieve the above object, the color correction apparatus of the time axis correcting apparatus of the present invention records video signal data for time axis correction in a memory, reads data from the memory according to the read clock and read reset signal, and outputs the video signal data. A time axis correction apparatus for time axis correction, comprising: lead clock generation means for generating a lead clock in accordance with a frequency of a reference color subcarrier; First reset signal generation means for generating a first reset signal obtained by dividing the read clock into a horizontal synchronization signal; Second reset signal generation means for generating a second reset signal for delaying the first reset signal by a half period of the color signal; And a read reset signal read reset signal selecting means for outputting one of the first and second reset signals in accordance with a reproduction mode to control data read from the memory.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of the digital time-base correction device according to the present invention. The crystal oscillator 26 generates a read clock of 4 fsc (fsc: 3.58 MHz at the color subcarrier frequency) and the light clock pulse generator 25 The voltage controlled oscillator generates a light clock with a reference frequency of 4fsc.

The sync signal separator 24 separates the horizontal sync signal H-SYNC, the vertical sync signal V-SYNC, and the frame signal from the input video signal.

The limit clock pulse generator 25 detects a time axis error with a horizontal synchronizing signal (H-SYNC), drives a voltage controlled oscillator of 4fsc to generate a light clock (WRT-CK), and divides the light clock into a horizontal synchronizing signal period. Then, a write reset (WRT-RST) signal is generated, and the output data of the A / D converter 21 is recorded in the memory 22.

The crystal oscillator 26 used as a read clock pulse generator generates a read clock RD-CK of 4 fsc, reads data from the memory 22 according to the read clock, and outputs the data to the D / A converter 23.

The color correction device 27 inverts the color signal phase at the frame period of the video signal of the still / throw player, and generates a read reset signal for correcting it to the same video signal as in normal playback.

The color correction device 27 generates the first reset signal RST-R1 during normal playback and the second reset signal RST-R2 during still / slow playback, and generates a selection signal SW-R. Accordingly, the memory 22 is controlled by selecting the read reset signal RST-R.

The first reset signal RST-R1 is a read reset signal RD-RST of the memory 22 during normal reproduction, and the read clock RD-CK of the crystal oscillator 26 is set to one horizontal synchronization signal period. / 910 division 271 is inputted to the read reset selector switch 273.

The second reset signal RST-R2 selects read reset by delaying the first read signal RST-R1 by two clocks in order to invert the phase of the color signal at a frame period during still / slow reproduction. It is input to the switch 273. When the read clock RD-CK is 4fsc, the 2 clock delay is a unit in which a half cycle of the color signal, that is, phase inversion occurs.

The control signal generator that generates a selection signal for controlling the read reset selection switch 273 in accordance with the regeneration mode is composed of a flip-flop and a divider.

The flip-flop 275 generates a pulse according to the signal according to the playback mode and the frame signal FRAME and the vertical synchronization signal V-SYNC, and the 1/2 divider 274 outputs the output pulse signal of the flip-flop 1. / 2 divide.

During normal playback, the output Q of the flip-flop 275 is always high (H) by the normal playback mode signal, so that the read reset select switch 273 selects and outputs the first reset signal.

During still / slow playback, the flip-flop 275 generates a pulse which is a frame period according to the vertical synchronization signal and the frame signal, and divides this pulse into 1/2 to change the high (H) and the low (L) periods in the frame period ( SW-R) can be obtained. Accordingly, the read reset select switch 273 alternately outputs the first reset signal RST-R1 and the first reset signal RST-R2 at frame periods to control the memory, thereby being read from the memory. The data becomes a video signal in which the color phase is inverted at the frame period.

In addition, one frame of the video signal is divided into two fields, that is, the odd and even fields, and the flip-flop is used to uniformly disc trace the odd field of the video signal. Through the pulse generator 276 for shaping the output signal of 275, a track jump sync signal, which is a sync signal of a disk track jump, is generated at a frame period.

3 is a waveform diagram related to the time-base correction device according to the present invention, in which 3A is a vertical synchronization signal (V-SYNC), 3B is a frame signal, 3C is an output signal Q of flip-flop 275, and 3D is a general The read reset selection signal SW-R at the time of reproduction, 3E are the read reset selection signals SW-R at the time of still / slow reproduction, and 3F are waveform diagrams of the track jump synchronous signal.

In normal playback, data recorded in the memory is always read out as the first read set signal, and data stored in the memory in the first and second read set signals are alternately changed according to the frame period during still / slow playback. To reverse the color phase.

The track jump synchronizing signal 3F is input to the microcomputer and used as a synchronizing signal for a disk track jump.

As described above, according to the present invention, a color correction circuit for generating the same video signal by inverting the color signal phase at the frame period of the video signal during still / throw reproduction can be prevented, thereby preventing the color change occurring during still / throw reproduction. This has an advantage.

Claims (7)

In the time-base correction device for recording the video signal data for time-base correction in memory, and reading the data from the memory according to the read clock and read-reset signal, according to the frequency of the reference color subcarrier. Lead clock generation means for generating a lead clock; Second reset signal generation means for generating a first reset signal obtained by dividing the read clock into a horizontal synchronization signal; Second reset signal generation means for generating a second reset signal for delaying the first reset signal by a half period of the color signal; And a read reset signal selecting means for outputting one of the first and second reset signals according to a reproducing means to generate a read reset signal for controlling data read of the memory. Color compensator of time base compensator. 2. The color compensating device of a time axis correcting apparatus according to claim 1, wherein said first set reset signal generating means generates a signal obtained by dividing the lead clock by 1/910. 2. The color compensating device of claim 1, wherein the read reset signal generating means generates a signal obtained by delaying the first reset signal by two periods. 2. The read reset signal selecting means according to claim 1, wherein the read reset signal selecting means generates a selection control signal for selecting the first reset signal in the normal reproduction mode, and the first reset signal in the still / throw reproduction mode. A control signal generator for generating a selection control signal for alternately selecting the second reset signal at a frame period; And a read reset selection switch configured to input the first reset signal and the second reset reset signal to generate a read reset signal according to the selection control signal. Color Corrector. 5. The apparatus of claim 4, wherein the control signal generator comprises: a flip flop for generating a pulse of a constant digital level in a normal reproducing mode and a pulse having a frame period according to the frame signal and the vertical synchronization signal in a still / slow reproducing mode; And a divider for dividing the period of the pulse generated in the flip flop by 1/2, and generating a selection control signal having a constant digital level in the normal reproducing mode, and a period of the pulse generated in the flip flop in the still / slow reproducing mode. Is divided by 1/2 to generate a selection control signal for changing the digital level at frame periods. 5. The time axis correction device according to claim 4, wherein the control signal generator shapes a pulse generated in the flip flop to further generate a track jump synchronous signal for jumping a disc track at a frame period during still / throw playback. Color corrector. An analog-digital converter for converting an input video signal into a digital signal; A digital-analog converter for converting the digital signal read out from the memory for recording and reading the digital signal into an analog signal; A synchronization signal separator generated by separating the horizontal synchronization signal, the vertical synchronization signal, and the frame signal from the input video signal; A light clock is generated according to the horizontal synchronous signal, the light clock is divided by a period of the horizontal synchronous signal to generate a light reset signal, and the output data of the analog-digital converter is converted into a predetermined amount of data in the memory. A light clock pulse generator for recording; A lead clock pulse generator generating a lead clock according to a frequency of the reference color subcarrier; And a first reset signal generating means for generating a first reset signal by dividing the read clock into a horizontal synchronization signal, and a second reset set delaying the first read signal by a half period of a color signal. A second reset signal generating means for generating a signal, and a read reset signal for controlling data readout of the memory by outputting one of the first and second reset signal in accordance with the reproduction mode. A color correction device having a read reset signal selecting means for generating a read reset signal for controlling data reading of said memory, said first reset signal being generated in a normal reproduction mode, And the first and second read set signals are alternately generated in a frame period in a slow regeneration mode.