KR950006056B1 - Revival error correction apparatus of image writing equipment - Google Patents

Abstract

The apparatus corrects the time axis error of the video cassette recorder and compensates the drop out error. The apparatus comprises: a write address generator unit reset by the horizontal synchronous signal; a memory control unit generating the write inhibition signal while the drop out is detected; a line memory outputting the image with the horizontal period; and a phase inversion unit inverting the color signal after receiving the line horizontal unit.

Description

Playback Error Correction Device of Video Recorder

1 is a block diagram of a device for correcting a conventional timebase error and dropout.

2 is a block diagram of an error correction apparatus for an image recording recorder according to the present invention.

3 is a configuration diagram of a timing controller of FIG. 2.

4 is an operating waveform diagram of each part of FIG.

* Explanation of symbols for main parts of the drawings

201: A / D converter 202: line memory

203: Light address generator 204: Memory control unit

205: lead address generator 206: error correction

207: bandpass filter 208: multiplier

209: Subtractor 210: Selector

The present invention relates to an apparatus for correcting a reproduction error of an image recorder, and more particularly, to an apparatus capable of compensating for correction and dropout of a time axis error by using the same memory during reproduction.

In general, a video recorder has been developed to record and play a video signal closer to an actual video. Such a video recorder includes a video disk player (VDP) and a video cassette recorder (Video Casstte). Recorder: VCR) is a representative device. When the video signal is reproduced by the video recorder, the reproduced video signal includes a fine time base error. When a video signal is recorded on the recording medium, a signal may be missed during recording due to a defect of the recording medium, and a drop out may occur. In this case, a dropout phenomenon may occur in which a synchronization signal is lost due to loss of a reproduction signal. Therefore, the video recorder includes time base correction and drop out compensation to correct the above error. 1 is a block diagram of an apparatus for compensating for the conventional time axis error correction and dropout as described above, and includes an A / D converter 101, a light control unit 102, a RAM 103, and a lead control unit 104. Corresponding to the time axis error correction unit, a portion composed of the line memory 105, the bandpass filter 106, the multiplier 107, the adder 108, and the selector 10 corresponds to the dropout compensator. First, a correction process of a time axis error is performed. The analog video signal reproduced from the recording medium is converted into digital video data by the A / D converter 101 and applied to the RAM 103. At this time, the write controller 102 generates a write clock pulse CKw synchronized with a color burst from the composite video signal to control the write operation of the RAM 103. That is, the write controller 102 generates a write clock pulse CKw synchronized with the color buster signal from the composite video signal and applies the write clock pulse CKw to the sampling clock of the A / D converter 101 and the write clock of the RAM 103. .

In addition, the image data stored in the RAM 103 is output by the read control unit 104 as described above. The read control unit 104 generates a read clock generated by the system reference clock by the reference color burst signal and the reference horizontal synchronization signal Href. CKr is supplied to the lead clock of the RAM 103. Therefore, the RAM 103 stores the image data reproduced by the light clock CKw synchronized with the color burst signal of the composite synchronization signal, and reads out the image data being stored by the read clock CKr generated from the system reference clock. It is to correct the time-base error that occurs minutely in the reproduction mode. In addition, referring to the dropout compensation process, the image data output from the RAM 103 is applied to the line memory 105 and to the B terminal of the selector 109. The image data stored in the line memory 106 is delayed by one horizontal line period and then applied to the A terminal of the selector 10. In this case, since the dropout detection signal is applied as the control signal of the selector 109, the selector 109 selects and outputs the image data of the RAM 103 received through the B terminal when the dropout signal is not applied. When the dropout signal is received, the dropout is compensated by selectively outputting the image data of the previous state delayed by one horizontal line through the line memory 105. The output of the line memory 106 is applied to one side input of the adder 108 and simultaneously applied to the band filter 106 to extract only the signals of the color signal band. The output of the bandpass filter 106 is multiplied by a predetermined integer value through the multiplier 107 and then applied to the remaining terminals of the adder 108. The adder 108 then subtracts the output of the multiplier 107 from the output of the line memory 106 and applies it to the A terminal of the selector 109. This is an operation process of phase inverting color signal components in the image data.

That is, the NTSC standard video signal is inverted by 180 degrees for each horizontal scan line. Therefore, when dropout detection is performed, the phase of the color signal component is inverted to replace the video signal before the one horizontal scan line with the current horizontal scan line. It is to be made.

However, as described above, a line memory is separately provided in a configuration of correcting a time axis error during reproduction in a conventional video recorder and compensating for dropout detection, thereby complicating control of the correction process and increasing the volume of the system. there was.

Accordingly, an object of the present invention is to provide an apparatus capable of compensating for an error using the same memory when correcting a time axis error and compensating for a dropout in an image recorder.

In order to achieve the object of the present invention, the present invention counts the sampling clock to generate one line of light addresses and is reset by the reference horizontal synchronization signal, and receives the dropout detection signal and the dropout detection signal. Memory control means for generating a write prohibition signal during the detected period, a lead address generating means by counting a read clock, and reset by a reference horizontal synchronization signal, and image data received by the write address; A line memory for storing the image data one line before the write inhibit signal and storing the image data stored by the read address in one line period when the write inhibit signal is received and the dropout detection period during the dropout detection. The dropout detection after storing the write address Means for generating a switching signal so that the color signal component of the line memory is phase inverted by controlling a corresponding read address, and means for receiving the output of the line memory and phase inverting the color signal, and a first terminal of the output terminal of the line memory. And a second terminal connected to the phase shifting means and configured to selectively output an output of the second terminal when the switching signal is generated.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 shows a configuration for compensating for time axis error correction and dropout according to the present invention. The A / D converter 201 receives a composite video signal, receives a write clock CKw as a sampling clock, and converts the composite video signal into digital image data. The light address generator 203 receives the light clock CKw and the horizontal synchronization signal Hsync, generates a light address for recording the image data of one horizontal line by counting the light clock CKw, and receives the horizontal synchronization signal Hsync. It is initialized every time. The memory controller 204 receives the dropout detection pulse, generates a write enable signal in the write mode, and outputs a write inhibit signal during the detection period when the dropout detection pulse is received. The read address generator 205 receives the reference lead clock CKr and the reference horizontal synchronization signal Href, counts the reference lead clock CKr to generate a read address of one horizontal line, and is initialized every time the reference horizontal synchronization signal Href is received. The line memory 202 receives the output of the memory control unit 204 as a control signal, receives the output of the write address generator 203 as a write address, and receives the output of the read address generator 205 as a read address. . The line memory 202 outputs the image data output from the A / D converter 201 to the write address position generated by the write address generator 203 when the memory control unit 204 outputs the write enable signal. The memory controller 204 stops the write operation when the memory controller 204 generates the write inhibit signal and maintains the storage state of the image data of the previous horizontal line.

Further, the video data recorded at the lead address position generated by the lead address generator 205 is read out and output. Therefore, the line memory 202 stores video data received by the light clock CKw synchronized with the composite video signal, and outputs the video data read by the reference read clock CKr of the system. It is possible to compensate the error of the existing time base. In addition, in the dropout detection section, since the write operation of the received image data is stopped and the image data of the previous horizontal line is maintained, in this state, the image data of the previous horizontal period of the lead address tm position designated by the lead address generator 205 in this state. You can see that is output. The error correction unit 206 receives a write address of the write address generator 203, a read address of the read address generator 205, and the dropout detection pulse, detects a dropout period, and outputs a corresponding dropout period. A switch signal is generated to invert the phase of the video signal. The band filter 207 receives the output of the line memory 202 and extracts data of a color signal band from the output image data. The multiplier 208 receives the multiplier 207 and multiplies the multiplier. The adder 209 receives the output of the line memory 202 and the output of the multiplier 208, and subtracts the output of the multiplier 208 from the output of the line memory 202 to generate a 180 degree phase inverted color signal. do. The selector 210 receives an output of the line memory 202 as a first terminal, an output of the adder 209 as a second terminal, and receives a switch control signal as an output of the error correction unit 206. Accordingly, the selector 210 selects and outputs the output of the line memory 202 in the normal state by the output of the error correction unit 206 and outputs the multiplier 208 in the dropout detection section. The video signal in which the color signal components are phase-inverted by 180 degrees among the video data of the period is selectively outputted.

3 is a detailed configuration diagram of the error correction unit 206 of FIG. 2, in which the flip-flop 301 receives the output of the write address generator 203 as data and clocks an inverted signal of the dropout detection pulse. To receive. The flip-flop 301 latches the write address of the corresponding time point as the start address of the dropout in the section where the dropout starts. In the flip-flop 302, the write address generator 203 receives an output as data and the dropout detection pulse as a clock. The flip-flop 301 latches the write address at the point in time at which the dropout ends, as the end address of the dropout. The comparator 303 receives the outputs of the flip-flop 301 and the flip-flop 302, receives the output of the lead address generator 205, and compares the write addresses with the read addresses of the dropout detection section at the time of writing. To generate a dropout section signal. The delay unit 304 receives the output of the comparator 303 and applies a switch control signal of the selector 210 by delaying the drop out section signal. The reset signal generating means receives an inverting delay unit 305 for delaying the inversion of the output of the comparator 303 by a predetermined time, an output of the comparator 303 and an output of the inverting delay unit 305, and the two inputs. The signal is negatively multiplied to generate a reset signal and then supplied to the flip-flop 301 and the flip-flop 302.

4 is an operation waveform diagram of each part of FIG. 3, where 4A is an output waveform diagram of the comparator 303, 4B is an output waveform diagram of the retarder 304, and 4C is an inverse delay. 4D is an output waveform diagram of the NAND gate 306.

The present invention will be described in detail with reference to the waveform diagram of FIG. 4 based on the configuration of FIG. 2 and FIG. 3 described above.

The light clock CKw is a pulse signal synchronized with the color burst signal of the composite video signal, and is applied to the sampling clock of the A / D converter 201 as a write clock to the write address generator 203. The light clock CKw becomes four times the frequency of the color carrier in the NTSC system. The A / D converter 201 receives a composite video signal, samples the composite video signal received by the light clock CKw, and converts the composite video signal into digital image data. At this time, the write address generator 203 receives and counts the light clock CKw to generate the write address of the line memory 202, and is initialized each time the horizontal synchronization signal Hsync is generated. Accordingly, the write address generator 203 is reset every time the horizontal synchronous signal Hsync is input to generate the write address by the light clock CKw. In this case, if the dropout detection pulse is not received, the memory controller 204 generates a write enable signal having a low logic. Therefore, when the write enable signal is received, the line memory 202 stores the image data received from the A / D converter 201 at a write address location output from the write address generator 203. In addition, the lead address generator 205 receives a reference lead clock CKr and a reference horizontal synchronization signal Href generated from a stable reference frequency generator, counts the lead clock at a period of the reference horizontal synchronization signal Href, and generates a lead address. Supply to memory 202. Therefore, the read address generator 205 generates the read addresses at every horizontal scan line period, thereby reading out the horizontal data of one horizontal line stored in the line memory 202. Accordingly, by using different clocks for the light clock CKw and the read clock, the error of the time axis that can be minutely generated can be compensated.

In such a state, the error correction unit 206 outputs a high logic switch control signal, so that the selector 210 selects and outputs the output of the line memory 202 received at the first terminal. The above operation process represents an operation in a normal state in which a dropout pulse is not detected.

However, when the dropout detection pulse is received, the memory controller 204 outputs a write control signal with a high logic to generate a write inhibit signal. At this time, since the write address generator 203 continuously counts the write clock CKw, the write address is continuously generated. In this case, since the line memory 202 receives the write prohibition signal from the memory control unit 204, the write operation is stopped and the image data corresponding to the previous horizontal scan line is stored in the region of the corresponding address. Accordingly, it can be seen that the image data read by the read address generator 205 becomes image data by the previous horizontal scanning line. When outputting the image data of the previous horizontal scanning line as described above, the color signal of the image signal should be output by inverting the phase by 180 degrees. This is because the color burst of the NTSC standard video signal has a 180 degree phase difference in every horizontal scanning line. Therefore, when dropout occurs, when the output image data is to be replaced with the image data of the previous horizontal scanning line stored in the line memory 202, the phase of the color signal component is reversed 180 degrees in the image data of the previous horizontal period. You have to. The phase shift means as described above is composed of a bandpass filter 207, a multiplier 208, and an adder 209. First, the band filter 207 receives image data of a previous horizontal scanning line output from the line memory 202 and extracts and outputs only a color signal component of a 3.58 MHz band.

The multiplier 208 multiplies the color signal received from the bandpass filter 207 by a predetermined integer. In the present invention, multiplication is performed twice. The multiplier 208 subtracts the output of the multiplier 208 from the output of the line memory 202 to invert the phase of the color signal in the image signal of the previous horizontal scan line and applies it to the second terminal of the selector 210. do. Then, when the switch control signal received from the error correction unit 206 is received with low logic, the selector 210 switches to the second terminal and selects and outputs an image signal outputting the multiplier 208. Compensate for the image in the section.

To this end, the error correction unit 206 should detect a section of the dropout signal and generate a switch control signal for outputting a phase-inverted image signal during the period. In this case, first, the dropout period should be detected. The flip-flop 301 receives the write address and receives the inverted signal of the dropout detection pulse by clicking to generate the write address at the point where the dropout starts. The flip-flop 302 receives the write address and receives the dropout detection pulse as a clock to generate a write address at the end of the dropout. Accordingly, the flip-flop 301 latches the light address at the time when the dropout starts, and the flip-flop 302 latches the light address at the end. The comparator 303 compares the write address outputting the flip-flop 301 with the read address outputting the lead address generator 205 and the write address and lead address generator 205 outputting the flip-flop 302. After comparing the read address outputting the output signal), the two control signals are logically combined to output a switch control signal starting at the point at which the dropout starts and ending at the point at which the dropout ends, such as 4A. do. Thereafter, the switch control signal is delayed by the delay unit 304 and applied to the control terminal of the selector 210. The delay reason serves to compensate for the time delay of the color signal phase inversion circuit. Accordingly, the selector 210 outputs the image signal of the previous horizontal scanning line inverted in phase during the dropout period by the switch control signal. As described above, after the control signal for phase inverting the color signal components is generated once by the dropout detection pulse, the switch control signal for phase inverting the color signal components for each line is prevented until the next dropout detection pulse is input. shall.

To this end, a reset pulse is generated. When a switch control signal such as (4A) is generated in a low state, it is delayed and inverted by the inversion delay unit 305 and converted to (4C), and the same as (4A). The NAND gate 306, which receives the output of the comparator 303 and the output of the inverting delay unit 305 such as 4C, generates a reset pulse such as 4D by applying a negative logic multiplication on the two received signals. The reset pulse is applied to the reset terminals of the flip-flop 301 and the flip-flop 302, thereby preventing the phase inversion control signal from being continuously generated in units of lines. Therefore, when the output of the flip-flop 301 and the flip-flop 302 at the rising edge of the switch control signal for reversing the phase of the color signal, the clock frequency of the addressing area 7 of the line memory 202 is four times the color carrier. By resetting to an address (for example, 910, etc.) other than the 0-909 address area, it is possible to prevent the comparator 303 from generating the switch control signal again.

As described above, the present invention does not need to have a separate time control unit in consideration of the delay of the time axis correction, which is a variable delay line, when compensating for the dropout when reproducing the video signal recorded in the video recording and recording, and sharing the ry memory. As a result, the memory can be efficiently used and the control unit can be shared.

Claims (2)

A device for correcting an error in a video recording recorder, wherein the sampling clock is counted to generate one line of light addresses, the light address generating means being reset by a horizontal synchronization signal, and a section in which a dropout is detected while receiving a dropout detection signal. Memory control means for generating a write prohibition signal, a read address generating means for counting a reference clock of the system and reset by the system horizontal synchronization signal, and image data received by the write address. The line which is lowered by the line period and is output by the lead address to correct a time axis error, and maintains the image data of the previous line as it is when receiving the write inhibit signal and outputs the image data of the previous horizontal period being stored by the lead address. Memory and a dropout interval when the dropout is detected. Means for generating a switching signal such that the color signal component of the line memory is phase inverted during a read address period corresponding to the dropout period after detecting the address address, and means for phase inverting the color signal by receiving the output of the line memory; And a first terminal connected to an output terminal of the line memory, a second terminal connected to the phase shifting means, and means for selectively outputting the output of the second terminal only when the switching signal is generated. Correction device. 2. The apparatus of claim 1, wherein the means for generating the switch signal receives the write address as data and the dropout signal as a clock to latch the write address as a start address at the time when the dropout signal starts. Means for latching the write address to the end address at the end of the dropout signal; and the selection means from the time at which the dropout starts to the end when the start and end write addresses and the read address are received and compared, respectively; And means for outputting a switch control signal and means for generating a reset signal for initializing the latch means by delaying the switch control signal by a predetermined delay.