KR0166921B1 - Protection circuit of screen quality deterionation - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for preventing deterioration of image quality appearing in a multi-channel recording and reproducing apparatus. Particularly, when a second vertical synchronization signal is generated, the second vertical synchronization signal is counted in synchronization with a clock and counted. When the position of the signal is the head switching occurs, the memory control unit is composed of a counter for generating a reset write signal and a reset read signal generator for generating a reset read signal by delaying the first vertical synchronizing signal for a predetermined time. By the write start time of the memory in which the second TV signal is written by matching the head switching time by the count of, the skew distortion that occurs twice occurs once near the head switching pulse, thereby preventing the image quality of the upper part of the screen from being deteriorated. Can be.

Description

Image deterioration prevention circuit in multi-channel recording and reproducing apparatus

1 is a block diagram showing signal processing during recording in a conventional multi-channel recording and reproducing apparatus.

2 is an operation timing diagram of each part of FIG.

3 is a view showing a deterioration of image quality according to FIG.

4 is a block diagram of an image deterioration prevention circuit in the multi-channel recording and reproducing apparatus according to the present invention.

5 is an operation timing diagram of each part of FIG. 4;

* Explanation of symbols for main parts of the drawings

101: first synchronous separator 102: second synchronous separator

104: clock generator 105: analog / digital converter

106: field memory 107: digital / analog converter

400: memory controller 41: counter

42: RSTR generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for preventing deterioration of image quality appearing in a multi-channel recording and reproducing apparatus capable of multi-channel recording and reproducing at one track pitch. In particular, the present invention relates to a video cassette recorder for recording and reproducing multiple channels. An image deterioration prevention circuit in a multi-channel recording / reproducing apparatus which prevents deterioration of image quality appearing at the upper part of image quality by using a head switching time of a VCR) and a memory control time of digital signal processing.

FIG. 1 is a block diagram showing signal processing at the time of recording in a conventional multi-channel recording and reproducing apparatus, wherein the first synchronous separation unit 101 separates the vertical synchronization signal from the main program (hereinafter, referred to as a first TV signal). , A second synchronization separator 102 for separating the vertical synchronization signal from a sub-program (hereinafter, referred to as a second TV signal), a clock generator 104 for generating a clock synchronized with the second TV signal by oscillation, and An analog / digital converter (ADC) 105 for converting a second TV signal into a digital signal generates a restart write signal (RSTW) in synchronization with a second vertical synchronous signal and generates a first vertical synchronous signal. A memory control unit 103 which generates a restart read signal RSTR in synchronization with the signal, and stores the digital data of the second TV converted by the ADC 105 by the restart write signal RSTW and restart restart signal Output digital data stored by A field memory 106, and the field memory, a digital / analog converter for converting and recording the digital data that is read out from the (106) into an analog data; consists of (Digital / Analog Converter DAC) (107).

In this case, the clock generated by the clock generator 104 is provided to the memory controller 103, the ADC 105, the field memory 106, and the DAC 107.

In the case where the first TV signal and the second TV signal independent in FIG. 1 configured as described above are recorded on one tape, the first synchronization separating unit 101 separates the vertical synchronization signal from the first TV signal and outputs the same to the memory controller 103. The second synchronization separator 102 separates the vertical synchronization signal of FIG. 2C from the second TV signal of FIG. 2A and outputs the vertical synchronization signal of FIG. 2C to the memory controller 103.

At this time, the memory controller 103 generates a restart write signal RSTW as shown in FIG. 4 (d) to the field memory 106 in synchronization with the second vertical synchronization signal, and is synchronized with the first vertical synchronization signal. A restart read signal RSTR is generated to the field memory 106. The clock generator 104 generates a clock synchronized with the second TV signal by oscillation and provides the clock controller 104 to the memory controller 103, the ADC 105, the field memory 106, and the DAC 107. In addition, the ADC 105 converts the second TV signal into a digital signal in synchronization with a clock generated by the clock generator 104.

Accordingly, the second digital TV signal converted by the ADC 105 is fielded by the restart write signal RSTW generated as shown in FIG. 2D in synchronization with the second vertical synchronizing signal by the memory controller 103. The data written to the memory 106 and written to the field memory 106 is read by the restart read signal RSTR generated in synchronization with the first vertical synchronizing signal in the memory controller 103 to be read by the DAC 107. Is output.

As a result, the field memory 106 outputs a second digital TV signal synchronized with the first vertical synchronization signal.

Thus, the DAC 107 converts the second digital TV signal into a second analog TV signal synchronized with the first TV signal and then writes it to tape.

In this case, since the first diagram described above uses a clock synchronized with the second TV signal, the time between the restart write signal RSTW and the next restart write signal RSTW is n × clock period.

However, since the first TV signal and the second TV signal are independent signals, two vertical synchronizations separated from the first and second TV signals are not equal in time. The restart read signal RSTR is generated in synchronization with the first TV signal. The distance between the signal RSTR and the next restart read signal RSTR is n × clock period ± α.

Therefore, the distance between the horizontal synchronization lines H7 and H8 where the restart write signal RSTW as shown in FIG. 2D after the field memory 106 passes is different from the distance of the other lines, that is, the horizontal synchronization line H7. Since the horizontal synchronization interval may become uneven, such as shortening or lengthening between H8 and H8, data may be left or shortened when data is read from the field memory 106. Therefore, a skew phenomenon occurs in the section between the horizontal synchronization lines H7 and H8 and affects the auto frequency control (AFC) of the TV.

In addition, when the signal is reproduced after recording, the head switching pulse is generated in the blanking section of the TV signal as shown in FIG.

At this time, a skew phenomenon occurs when the head switching pulse is generated due to the tension of the tape, which also affects the AFC.

Here, the skew phenomenon means that the image is distorted as shown in FIG. 3, and the color variation section is shifted from the original position so that accurate color is not reproduced.

In this case, since the skew distortion is generated by the restart light signal generated at the rear end of the second vertical synchronization signal in addition to the skew generated by the head switching pulse, the color shift section moves to the upper portion of the screen as shown in FIG. There was a problem that the image quality of the upper screen is deteriorated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to generate a restart write signal for writing a TV signal in a field memory at a time point similar to when the head switching pulse is generated, so that skew distortion is near the head switching pulse. It is provided to prevent the deterioration of the image quality of the multi-channel recording and reproducing apparatus by causing it to occur only once.

A characteristic of the image quality deterioration prevention circuit of the multi-channel recording and reproducing apparatus according to the present invention for achieving the above object is that a second vertical synchronization signal is counted in synchronization with a clock when the second vertical synchronization signal is generated, and then counted. The memory control unit includes a count for generating a restart write signal and a restart read signal generator for generating a restart read signal by delaying the first vertical sync signal for a predetermined time when the position of the vertical synchronization signal is at the time of head switching occurrence. .

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram of an image deterioration prevention circuit of a multi-channel recording and reproducing apparatus according to the present invention, in which a first synchronization separating unit 101 which separates a vertical synchronization signal from a first TV signal and a vertical synchronization signal from a second TV signal A second synchronization separator 102, a clock generator 104 for generating a clock synchronized with the second TV signal by oscillation, an ADC 105 for converting the second TV signal into a digital signal, and a second vertical synchronization signal. The memory controller 400 generates a restart write signal RSTW at a time similar to the occurrence of the head switching time, and generates a restart read signal RSTR in synchronization with the first vertical synchronization signal. A field memory 106 for writing the digital data of the ADC 105 by a write signal RSTW and outputting the digital data written by the restart read signal, and a digital data read from the field memory 106. The DAC 107 converts data into analog data and records the data.

In this case, the memory controller 400 is synchronized with a clock to count the second vertical synchronization signal until the next head switching occurs and generates a restart write signal (RSTW) at a point similar to the time when the head switching signal occurs. And an RSTR generator 402 for generating a restart read signal RSTR synchronized with the first vertical synchronization signal.

Here, the clock generated by the clock generator 104 is provided to the memory controller 400, the ADC 105, the field memory 106, and the DAC 107.

When the independent first TV signal and the second TV signal are recorded on one tape in the present invention configured as described above, the first synchronous separation unit 101 separates the vertical synchronization signal from the first TV signal and outputs it to the memory controller 400. The second synchronization separator 102 separates the vertical synchronization signal of FIG. 5C from the second TV signal of FIG. 5A and outputs the vertical synchronization signal of FIG. 5C to the memory controller 400.

At this time, the counter 401 of the memory controller 400 counts the second vertical synchronizing signal in synchronization with a clock signal and when the counted value reaches the head switching pulse generating position value as shown in FIG. Is generated, the restart write signal RSTW is generated to the field memory 106 as shown in FIG. 5 (d), and the RSTR generator 402 delays the clock by the desired amount from the first vertical synchronization signal. A start read signal RSTR is generated to the field memory 106.

The clock generator 104 generates a clock synchronized with the second TV signal by oscillation, and provides the clock to the memory controller 400, the ADC 105, the field memory 106, and the DAC 107.

In addition, the ADC 105 converts the second TV signal into a digital signal in synchronization with a clock generated by the clock generator 104.

Accordingly, the second digital TV signal converted by the ADC 105 is a restart write signal generated at the counter 401 of the memory controller 400 in accordance with the head switching pulse generation time, as shown in FIG. Since it is written to the field memory 106 by RSTW, the time difference between the first TV signal and the second TV time appears at the time of the head switching pulse generation.

The data written to the field memory 106 is read by the restart read signal RSTR generated by the RSTR generator 402 of the memory controller 400 in synchronization with the first vertical synchronizing signal. Will be printed).

As a result, the field memory 106 outputs a second digital TV signal synchronized with the first vertical synchronization signal.

Therefore, the DAC 107 converts the second digital TV signal into a first analog TV signal synchronized with the first TV signal and then records it on a tape.

As described above, according to the image deterioration prevention circuit of the digital recording and reproducing apparatus, the write start time of the memory in which the second TV signal is written by the count of the vertical synchronization signal of the second TV is similar to the head switching pulse generation time. In this case, since the skew distortion that occurred twice occurs once in the vicinity of the head switching pulse, the image quality of the upper portion of the screen does not deteriorate.

Claims (1)

A first synchronous separator for separating a vertical synchronous signal from a first TV signal, a second synchronous separator for separating a vertical synchronous signal from a second TV signal, an analog / digital converter for converting the second TV signal into a digital signal; A memory control unit generating a restart write signal and a restart read signal for writing and reading the second TV signal converted into a digital signal; and a second TV converted into the digital signal by a restart write signal output from the memory control unit. A field memory for storing a signal or reading and storing a stored second TV signal by the restart read signal, and a digital / analog converter for converting the second TV signal read from the field memory into an analog signal and recording the result in a recording medium; Generates a clock synchronized with a second TV signal, so that the memory controller, analog / digital converter, In a multi-channel recording and reproducing apparatus comprising a clock and a clock generator provided to a digital / analog converter, the memory controller synchronizes the second vertical synchronous signal to a clock when a second vertical synchronous signal is generated. When the position of the second vertical synchronization signal, which is counted and counted, is at the point of head switching occurrence, the counter generates a restart write signal, and the restart read signal generator generates a restart read signal by delaying the first vertical synchronization signal for a predetermined time. And a deterioration prevention image quality in a multi-channel recording and reproducing apparatus, characterized in that the invention is made.