JPH08172608A - Video signal processing unit - Google Patents

Abstract

PURPOSE: To precisely attain recording onto a recording medium by writing data into an image memory even when a large fluctuation exists in an input video signal, reading out data from the image memory stably and conducting the succeeding process surely and efficiently. CONSTITUTION: A clock signal synchronously with a horizontal synchronizing signal in an input video signal is generated by a high speed response PLL circuit 13 and an A/D converter 5 converts the signal into a digital signal according to the clock signal and writes the signal in an image memory 6 based on the clock signal. The clock signal synchronously with a vertical synchronizing signal in the input video signal is generated by a low speed response PLL circuit 15 and data are read out from the image memory 6 according to the clock signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing device capable of coping with an input video signal having a jitter in a device for highly efficiently encoding image information for recording.

[0002]

2. Description of the Related Art In a conventional video signal processing apparatus, an input video signal having a jitter is processed by an A / D converter and an image memory. FIG. 4 shows a block diagram of a conventional video signal processing device. In the figure, 1 is an input terminal of a video signal. Reference numeral 2 is a sync separation circuit for separating a vertical sync signal and a horizontal sync signal from the input video signal. Reference numeral 3 is a control signal generation circuit for generating a reference signal (vertical reference signal, horizontal reference signal) based on the vertical synchronization signal and horizontal synchronization signal separated by the synchronization separation circuit 3.

A PLL 4 receives a reference signal (horizontal reference signal) generated by the control signal generating circuit 3 and generates a clock which is phase-synchronized with the input video signal by following the fluctuation.
A circuit that generates a voltage-controlled oscillator that generates a clock, a divider that divides the clock, a phase comparator that compares the phase of the reference signal and the output of the divider, and a low-frequency component of the output of the phase comparator that is extracted. It has a built-in low-pass filter that supplies voltage-controlled oscillators. Reference numeral 5 is an A / D converter for analog-digital converting the input video signal.

An image memory 6 can store at least one field of data. Reference numeral 7 is a write control circuit that controls writing of the output data signal of the A / D converter 5 into the image memory 6 based on the clock and the reference signal. 8 is an image memory 6 based on a clock and a reference signal
It is a read control circuit for controlling the read of the data stored in the memory. Reference numeral 9 is a processing block for performing arbitrary processing on the data output from the image memory 6. Reference numeral 10 is an output terminal for the data output from the processing block 9.
Reference numeral 11 is an output terminal of a reference signal of a control circuit such as a servo circuit for controlling the relative position of a recording head and a recording medium of an apparatus for performing highly efficient encoding of image information for recording.

The operation of the video signal processing apparatus configured as described above will be described below with reference to FIG. The sync separation circuit 2 separates the vertical sync signal and the horizontal sync signal from the input video signal applied to the input terminal 1, and the control signal generation circuit 3 generates a reference signal (vertical reference signal, horizontal reference signal). The horizontal reference signal of the reference signals is a PLL
The clock input to the circuit 4 and synchronized with the input video signal is generated. The input video signal is analog-digital converted by the A / D converter 5 and input to the image memory 6 as image data. Further, the reference signal and the clock are input to the writing control circuit 7, and the writing control circuit 7 creates a control signal for controlling writing in the image memory 6,
It is input to the image memory 6, and writing of image data is controlled by this.

Regarding the reading of data from the image memory 6, a read control circuit 8 creates a read control signal based on the reference signal of the control signal generation circuit 3, and the data is sequentially supplied from the image memory 6 to the processing block 9. Then, after being processed in the processing block 9, the signal is output from the output terminal 10. Further, the control signal generation circuit 3 outputs the reference signal of the servo circuit generated from the vertical synchronizing signal in the input video signal. In a device that performs high-efficiency encoding of image information and performs recording, the relative position of the recording head and the recording medium is controlled by a servo circuit, and the image data output from the terminal 10 is recorded in advance on a recording medium such as a magnetic tape or a disk. It is recorded at the determined position.

[0007]

However, in the above-mentioned conventional configuration, such as a video signal having a large jitter, a video signal in which the horizontal frequency and the vertical frequency are not in a normal relationship, or a signal reproduced from a home VTR. When a signal with a discontinuity (skew) in the horizontal sync signal, or a signal reproduced from a tape recorded in a state where synchronization disturbance occurs due to the large vibration that sometimes occurs during shooting with a home movie VTR, the horizontal frequency is input. Since the vertical frequency and the clock frequency cannot be synchronized with each other, there is a problem in that when reading from the image memory, the relative fluctuation of the data with respect to the input video signal becomes large and stable signal processing cannot be performed. Was there.

The present invention solves the above-mentioned problems of the prior art. Even if there is a large fluctuation in the input video signal, the writing of data to the image memory and the reading of data from the image memory can be performed stably. SUMMARY OF THE INVENTION It is an object of the present invention to provide a video signal processing device capable of surely and efficiently performing the above processing and accurately recording on a recording medium.

[0009]

In order to achieve this object, a video signal processing device according to a first aspect of the present invention provides a first vertical reference signal based on a vertical sync signal and a horizontal sync signal in an input video signal. A first control signal generation circuit for generating A1 and a horizontal reference signal A2, and a high-speed response PLL circuit for inputting the horizontal reference signal A2 and generating a first clock A3 phase-synchronized with the horizontal synchronization signal in the input video signal. , An A / D converter for sampling an input video signal at a first clock A3 and performing analog-to-digital conversion, an image memory capable of accumulating at least one field of data, a first clock A3 and a first vertical reference signal A write control circuit for controlling writing of a data signal, which is an output signal of the A / D converter, into the image memory with reference to A1 and the horizontal reference signal A2;
The second vertical reference signal B1 is generated by dividing the frequency of the second clock B3.
And a second control signal generation circuit B for generating a read reference signal B4, and a phase comparison between the first vertical reference signal A1 and the second vertical reference signal B1 to sufficiently narrow the band of the phase comparison signal. A low-speed response PLL circuit that forms a second clock B3 by forming a phase-locked loop whose response to an error variation is sufficiently slow, and data stored in an image memory with reference to the second clock B3 and the read reference signal B4. And a processing block for processing data output from the image memory.

A video signal processing device according to a second aspect is the video signal processing device according to the first aspect, in which a high-speed response PLL is used.
The circuit includes a clock oscillating circuit for generating a signal having a predetermined frequency, and a clock phase shift circuit for phase-shifting the output signal of the clock oscillating circuit to generate a clock that follows the fluctuation of the horizontal synchronizing signal. A video signal processing apparatus according to a third aspect is the video signal processing apparatus according to the first aspect, wherein the image memory has a data rearrangement processing function.

According to a fourth aspect of the present invention, there is provided a video signal processing apparatus which produces a first vertical reference signal A1 and a first horizontal reference signal A2 with reference to a vertical synchronization signal and a horizontal synchronization signal in an input video signal. Control signal generating circuit, a clock oscillating circuit for generating a stable first clock C3 with a constant frequency, a first horizontal reference signal A2 and a first clock C3 as inputs, and a fluctuation of the first horizontal reference signal A2. A clock phase shift circuit for phase-shifting the first clock C3 to generate a second clock A3 which is phase-synchronized with the horizontal synchronizing signal in the input video signal, and the input video signal to the second clock A3.
A / to perform analog-to-digital conversion by sampling at
The D converter, the first vertical reference signal A1, the first horizontal reference signal A2, and the second clock A3 while keeping the relative timing of the first data signal A5 which is the output signal of the A / D converter constant. From the first to the first clock C3 by performing clock phase conversion to the second vertical reference signal C1 and the second horizontal reference signal C2.
And a clock phase conversion circuit that generates a second data signal C5, a first processing block that processes the second data signal C5 output from the clock phase conversion circuit, and at least one field of data can be stored. An image memory having a rearrangement function, and writing for controlling writing of the second data signal C5 into the image memory on the basis of the first clock C3, the second vertical reference signal C1 and the second horizontal reference signal C2. A control circuit, and a third vertical reference signal B1 and a read reference signal B4 to which the third clock B3 is input.
And a second control signal generation circuit for generating the phase comparison between the first vertical reference signal A1 and the third vertical reference signal B1 to sufficiently narrow the band of the phase comparison signal, thereby sufficiently responding to the error fluctuation. A slow response PLL circuit that forms a slow phase locked loop and generates a third clock B3;
A read control circuit for controlling the read of the data stored in the image memory based on the third clock B3 and the read reference signal B4, and a second processing block for processing the data output from the image memory are provided. There is.

A video signal processing device according to a fifth aspect is the video signal processing device according to the first or fourth aspect, wherein
It is characterized in that a reference signal of a control circuit for controlling the relative relationship between the recording head and the recording medium is output from the second control signal generation circuit.

[0013]

According to the structure of the first aspect, even if the input video signal has a large fluctuation, the input video signal can be made into a high-speed response PLL.
The first clock A3 generated by the circuit is converted into a digital signal by the first clock A3 and is written into the image memory, and the second clock B3 generated by the low-speed PLL circuit is synchronized with the vertical synchronization signal and is stable.

According to the structure of the second aspect, the influence of the fluctuation of the horizontal synchronizing signal in the input video signal is limited to the horizontal period. According to the structure of claim 3, data can be rearranged in the same image memory. According to the structure of claim 4, even if the input video signal has a large fluctuation, the first video signal having a stable constant frequency is generated by the high-speed response PLL circuit including the clock oscillation circuit and the clock phase shift circuit. The clock C3 is phase-shifted to be converted into a digital signal by a second clock A3 which is phase-synchronized with the horizontal synchronizing signal in the input video signal, and the digital signal is clock-phase converted, and then is transferred to the image memory by the first clock C3. Writing is performed at the third clock B3 which is created by the low-speed PLL circuit and is synchronized with the vertical synchronizing signal and is stable.

According to the fifth aspect of the invention, the control circuit for controlling the relative relationship between the recording head and the recording medium operates according to the reference signal of the second control signal generating circuit.
The processed data is recorded at the correct position on the recording medium.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a video signal processing apparatus according to the first embodiment of the present invention. In the figure, 1 is an input terminal of a video signal. Reference numeral 2 is a sync separation circuit for separating a vertical sync signal and a horizontal sync signal from the input video signal. Reference numeral 12 is a first control signal generation circuit that generates a vertical reference signal A1 and a horizontal reference signal A2 with reference to the vertical synchronization signal and the horizontal synchronization signal.

Reference numeral 13 denotes a high-speed response PLL circuit which receives the horizontal reference signal A2 as input and generates a clock A3 that is phase-synchronized with the horizontal synchronizing signal in the input video signal by following the change at high speed. Oscillator, divider for dividing clock, phase comparator for comparing phase of reference signal and divider output, low-pass filter for extracting low frequency component of output of phase comparator and supplying to voltage controlled oscillator, etc. Built-in. Reference numeral 5 is an A / D converter that performs analog-digital conversion by sampling the input video signal with the clock A3.

Reference numeral 6 is an image memory capable of accumulating at least one field of data. 7 is an A / D based on the clock A3, the vertical reference signal A1 and the horizontal reference signal A2
It is a write control circuit that controls writing of the output data signal of the converter 5 into the image memory 6. 14 is clock B
3 is an input and the clock B3 is divided to obtain a vertical reference signal B1.
And a second control signal generation circuit B for generating a read reference signal B4. 15 is the first control signal generation circuit 1
2 from the vertical reference signal A1 and the second control signal generation circuit 1
A low-speed response PLL circuit that generates a clock B3 by forming a phase-locked loop whose response to an error variation is sufficiently slow by performing phase comparison with the vertical reference signal B1 from 4 and narrowing the band of the phase comparison signal, Built-in voltage-controlled oscillator that generates a clock, phase comparator that performs phase comparison between vertical reference signal A1 and vertical reference signal B1, low-pass filter that extracts the low-frequency component of the output of the phase comparator and supplies it to the voltage-controlled oscillator are doing. Reference numeral 8 denotes a read control circuit for controlling the read of the data stored in the image memory 6 based on the clock B3 and the read reference signal B4. A processing block 9 processes the data output from the image memory 6. Reference numeral 10 is an output terminal for the data output from the processing block 9. Reference numeral 11 is an output terminal of a reference signal of a control circuit such as a servo circuit for controlling the relative position of a recording head and a recording medium of an apparatus for performing highly efficient encoding of image information for recording.

The operation of the video signal processing apparatus of the first embodiment constructed as above will be described below with reference to FIG. From the input video signal supplied to the input terminal 1,
The sync separation circuit 2 separates the vertical sync signal and the horizontal sync signal, and the first control signal generation circuit 12 performs processing such as noise removal and timing adjustment to generate a vertical reference signal A1 and a horizontal reference signal A2. . The horizontal reference signal A2 is input to the high-speed response PLL circuit 13, and a clock A3 that follows the fluctuation of the horizontal synchronizing signal in the input video signal is generated.

The input video signal is converted into a digital signal by the A / D converter 5 using the clock A3, and is input to the image memory 6 as image data. Also, the vertical reference signal A
1, the horizontal reference signal A2, and the clock A3 are input to the writing control circuit 7, and the writing control circuit 7 creates a control signal for controlling writing in the image memory 6,
And the writing of the output data of the A / D converter 5 into the image memory 6 is controlled.

Next, the second control signal generating circuit 14 and the low speed response PLL circuit 15 form a phase locked loop. The vertical reference signal A1 output from the first control signal generation circuit 12 and the low-speed response P in the second control signal generation circuit 14
The low-speed response PLL circuit 15 compares the phase with the vertical reference signal B1 generated by dividing the clock B3, which is the output of the LL circuit 15, and limits the band of the low-pass filter that allows the phase comparison signal to pass sufficiently. A phase-locked loop having a slow response to an error variation is formed, and the low-speed response PLL circuit 15 outputs a sufficiently stable clock B3, which is synchronized with the vertical synchronizing signal in the input video signal, and this clock B3 is the first clock. 2 is supplied to the control signal generation circuit 14.

Next, the read control circuit 8 controls the read of the image memory 6 based on the read reference signal B4 output from the second control signal generation circuit B14.
The data output from the image memory 6 is processed by the processing block 9
After being processed in step 1, the data is output from the output terminal 10 as data. Here, the read reference signal B4 is a reference for reading from the image memory, the cycle is one field, one frame, or another arbitrary cycle, and a necessary phase difference with respect to the vertical reference signal A1 or the vertical reference signal B1 is obtained. I have it.

Further, the reference signal of the servo circuit produced by the first control signal generating circuit 12 is output from the output terminal 11. In a device such as a VTR or a disk device that performs high-efficiency encoding of image information for recording, the relative position of the recording head and the recording medium is controlled by a servo circuit, and the recording head is processed by the processing block 9 based on the positional information of the recording head. A recording signal is output, and the image data or the like output from the terminal 10 is recorded as a predetermined signal at a predetermined position on a recording medium such as a magnetic tape or a disk.

As described above, according to this embodiment, the fast response PLL circuit 13 for generating the clock A3 synchronized with the horizontal synchronizing signal in the input video signal and the clock B3 synchronized with the vertical synchronizing signal are provided. By providing the low-speed response PLL circuit 15 that generates a slow response, converting the input video signal into a digital signal at the clock A3 and writing the digital signal into the image memory 6, and reading the data from the image memory 6 at the clock B3, a large input video signal is obtained. Even if there is a change, subsequent processing can be performed reliably and efficiently. That is, since the clock of the processing block 9 is synchronized with the vertical synchronizing signal, the number of clocks for one field or one frame of the input video signal (usually the number of data in one horizontal scanning period and one vertical scanning period is constant) is constant. And especially,
When performing field processing, frame processing, or several frames collectively, it is not necessary to provide a margin such as a blanking period for signal processing of the processing block 9, that is, data compression, error correction code addition, modulation, etc. Can be effectively used in time-division processing.

Even if the signal is a non-standard signal, for example, a signal in which the ratio of the vertical synchronizing signal to the horizontal synchronizing signal is not a normal value, the frequency of the vertical synchronizing signal, or the signal having a large phase variation, most of the variation component is the image. Can be absorbed in memory 6,
The data can be stably output from the image memory 6 and the subsequent processing can be reliably performed. Moreover, this image memory 6
Can be used for rearranging data, so-called shuffling function, etc.

Here, the shuffling function is to make the image quality of the compressed image uniform when recording and reproducing the image information with high efficiency coding, and to perform dropout and special reproduction (slow, still, fast-forward). , Rewinding reproduction) is a function of changing the order of data in order to disperse the influence of code errors. For the shuffling function, one field unit and one frame unit can be considered. However, even if it is in units of 1 field or 1 frame, it is not always 1
It does not require a storage capacity for one field or one field. When a general-purpose memory is used as the image memory, the capacity value is predetermined such as 1 Mbit, 4 Mbit, etc., so that 100% effective use is rare, and a considerable amount of waste is always generated. The amount available for this jitter absorption reaches several tens of horizontal scanning periods in an actual implementation.

According to the present invention, this surplus can be effectively utilized for jitter absorption. The horizontal scanning period of several tens is sufficient as the memory capacity of a general time axis correction device. The relationship with jitter absorption will be described. The video signal processing device of the present invention is a kind of time base correction device.
The fast response PLL responds to the jitter of the input signal, and the signal from which the jitter is removed is taken out from the image memory. In the analog recording video tape recorder, the time axis is corrected at the time of reproduction, but in a device for recording in the state of a digital signal, it is necessary to absorb the jitter at the time of analog / digital conversion. This is because the phase information such as the horizontal synchronizing signal, which is the reference for jitter detection, is discarded during high-efficiency encoding, and there is no means for detecting jitter during reproduction.

Further, since the read timing of the image memory and the servo circuit are synchronized, the change in the read timing of the image memory and the timing of the signal sent to the print head are only the change of the print head, so the margin of the buffer memory is reduced. be able to. Further, when the input signal is switched, the phase of the vertical video signal of the input video signal becomes discontinuous. If this is input to the servo circuit as it is, if the amount of discontinuity is large, the control of the recording head is disturbed, and the signal from the processing block 9 may not be correctly recorded on the recording medium. When the response of the low-speed response PLL circuit 15 is delayed to such an extent that the response of the servo circuit is not significantly affected, the disturbance of the servo circuit can be prevented.

FIG. 2 shows a second embodiment of the present invention in which the structure of the fast response PLL circuit 13 of FIG. 1 is different from that of a general PLL circuit.
The first embodiment except the high-speed response PLL circuit 13
This is the same as the embodiment. The fast response PLL circuit 13 in the above-described first embodiment is generally composed of a voltage controlled oscillator, a frequency divider, a phase comparator, a low pass filter, etc., receives the horizontal reference signal A2 as an input, and has a frequency of a clock A3, The phase is proportional to the frequency of the horizontal reference signal A2, and the phase is synchronized.

On the other hand, FIG. 2 uses a high-speed response PLL circuit in which the frequency is constant regardless of the horizontal synchronizing signal and only the phase is synchronized with the horizontal synchronizing signal. In the figure, 16 is an input terminal for the horizontal reference signal A2. Reference numeral 17 is a clock oscillation circuit that oscillates a stable clock C3 having a constant frequency. Reference numeral 18 denotes a clock phase shift circuit that outputs a clock A3 that is phase-shifted by synchronizing the clock C3 with the phase of the horizontal reference signal A2. Reference numeral 19 is an output terminal of the clock A3. Reference numeral 20 is an output terminal of the clock C3.

In the case of a PLL in which the frequency and the phase change, there is no problem if the horizontal reference signal A2 is stable, but if there is a large phase shift such as noise inclusion or loss, or skew, phase disturbance continues for a certain period of time. In the method using the clock C3, the disturbance of one horizontal synchronizing signal is limited to one horizontal scanning period, and the disturbance of the timing of writing to the image memory can be minimized.

FIG. 3 is a block diagram of a video signal processing apparatus showing a third embodiment of the present invention. In the figure, 1 is an input terminal of a video signal. Reference numeral 2 is a sync separation circuit.
Reference numeral 12 is a first control signal generation circuit. Reference numeral 5 is an A / D converter. Reference numeral 6 is an image memory. Reference numeral 7 is a write control circuit. 14 is a second control signal generation circuit. 15
Is a low-speed response PLL circuit. Reference numeral 8 is a read control circuit. Reference numeral 9 is a processing block. Reference numeral 10 is a data output terminal. The above is the same as the configuration of FIG.

The difference from FIG. 1 is that the high-speed response PLL of FIG.
Instead of the circuit 13, the clock oscillation circuit 17 and the clock phase shift circuit 1 that oscillate the fixed clock described in FIG.
8 is used as a high-speed response PLL circuit, and a clock phase conversion circuit 21, a processing block 22, and an image data output terminal 23 are provided after the A / D converter 5. The operation of the video signal processing device configured as described above will be described below. The vertical separation signal and the horizontal synchronization signal are separated from the input video signal supplied to the input terminal 1 by the sync separation circuit 2, and the first control signal generation circuit 12 performs noise removal, timing adjustment, and other processing, and the vertical sync signal is generated. A reference signal A1 and a horizontal reference signal A2 are generated.

The clock oscillation circuit 17 outputs a stable clock C3 having a constant frequency. The horizontal reference signal A2 is input to the clock phase shift circuit 18 from the first control signal generation circuit 12, the clock C3 is phase-shifted in synchronization with the phase of the horizontal reference signal A2, and the horizontal synchronization signal in the input video signal is input. The clock A3 that follows the fluctuation of Here, the clock A3 is a signal that is continuous for one horizontal scanning period, but the phase shift amount changes every time the horizontal reference signal A2 is input, and discontinuity occurs.

The input video signal is converted into a digital signal by the A / D converter 5 using the clock A3. The clock phase conversion circuit 21 converts the clock of the output signal of the A / D converter 5 operating at the clock A3 in which discontinuity occurs into the clock C3 which is a continuous signal,
Vertical reference signal A1, horizontal reference signal A2, and A / D converter 5
The clock phase conversion from the clock A3 to the clock C3 is performed while keeping the relative timing of the data signal A, which is an output signal of, to the vertical reference signal C1, the horizontal reference signal C2, and the data signal C.

Next, the vertical reference signal C1, the horizontal reference signal C2, and the clock C3 are input to the write control circuit 7,
A control signal for controlling the writing of the image memory 6 is created by the writing control circuit 7 and input to the image memory 6, whereby the writing of the output signal of the clock phase conversion circuit 21 to the image memory 6 is controlled. The operation of the portion read from the image memory 6 is the same as in FIG.

On the other hand, the data output from the clock phase conversion circuit 21 is processed by the processing block 22,
The image data is output from the output terminal 23. As described above, according to this embodiment, the clock oscillation circuit 17, the clock phase shift circuit 18, and the clock phase conversion circuit 21.
By providing the following, the following effects can be obtained.

When signal processing is required between the A / D converter 5 and the image memory 6, a delay occurs. When the delay of the image data is longer than the blanking period of the video signal and the valid image data is located at the discontinuous point of the clock A3, the data may not be transmitted. Solve by converting to. Further, the clock of the write control circuit 7 becomes continuous, and the operation becomes stable.

Further, the input video signal is a luminance signal (Y signal) and color difference signals (RY, BY signals) or R, G,
In the case of the B signal, it may be desired to monitor this input signal as a composite signal encoded. The frequency accuracy and stability are required for the subcarrier signal required for encoding the color signal, but the clock oscillation circuit 17
Can be used as a reference signal for generating a subcarrier by using a crystal oscillation circuit, and since the clock of the encoder circuit is a continuous signal, it is possible to perform all encoding processing in the processing block 22, An analog video signal can be obtained by directly connecting the D / A converter to the output terminal 18.

The other effects are similar to those of the above embodiment.

[0041]

According to the video signal processing device of the present invention,
By providing the high-speed response PLL circuit and the low-speed response PLL circuit, a non-standard signal, for example, a signal in which the ratio of the vertical synchronizing signal and the horizontal synchronizing signal is not a normal value, the frequency of the vertical synchronizing signal,
Even if the signal has a large phase fluctuation, most of the fluctuation component can be absorbed in the image memory, data can be stably output from the image memory, and the subsequent processing can be reliably performed. Moreover, this image memory can be shared with the so-called shuffling function for rearranging the data.

Even with the shuffling function in units of one field and one frame, the storage capacity for one field and one frame is not necessarily required. As image memory,
When a general-purpose memory is used, its capacity is predetermined, so it is rarely possible to use it 100% effectively, and a considerably large amount of waste is generated. According to the present invention, this surplus can be effectively utilized for jitter absorption.

Further, by synchronizing the low-speed response PLL circuit with the vertical synchronizing signal, the clock of the processing block is synchronized with the vertical synchronizing signal, so that the number of clocks for one field or one frame of the input video signal becomes constant,
Especially, in a processing block that performs field processing or frame processing, it is not necessary to provide a margin such as a blanking period for signal processing such as data compression, error correction code addition, and modulation, and the circuit can be effectively used in time division processing. You can

Further, since the read timing of the image memory and the servo circuit are synchronized, the fluctuation of the read timing of the image memory and the timing of the signal sent to the recording head are only the fluctuation of the recording head, so that the margin of the buffer memory is reduced. be able to. Further, when the input signal is switched, the phase of the vertical video signal of the input video signal becomes discontinuous. If this is input to the servo circuit as it is, if the amount of discontinuity is large, the control of the recording head is disturbed, and the signal from the processing block may not be correctly recorded on the recording medium. If the response of the low-speed response PLL circuit is delayed to such an extent that it does not significantly affect the response of the control circuit that controls the relative relationship between the print head and the print medium, disturbance of the control circuit can be prevented.

Further, when the output clock of the high-speed response PLL circuit is discontinuous in the vicinity of the phase comparison with the horizontal synchronizing signal, or when the horizontal synchronizing signal has a large phase shift such as noise inclusion or loss, or skew, Although there is a drawback that the phase disturbance lasts for a certain period of time, if a configuration in which a constant clock is phase-shifted in synchronization with the horizontal synchronizing signal of the input video signal is selected as the high-speed response PLL circuit, the disturbance of one horizontal synchronizing signal is one horizontal. It is limited to only the scanning period, and it is possible to minimize the timing disturbance of writing to the image memory.

In addition, by providing the clock phase conversion circuit, the clock of the data signal output from the A / D converter can be converted into a constant clock, and the clock of the write control circuit becomes a continuous signal. It is possible to avoid malfunction due to discontinuity of. Further, since the clock frequency is constant and the phase is continuous, signal processing such as encoding processing is performed, and in the state of a digital signal, it is converted into an NTSC system or PAL system color video signal,
It can be D / A converted and output.

[Brief description of drawings]

FIG. 1 is a block diagram of a video signal processing device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of an essential part of a second embodiment in which the configuration of the high-speed response PLL circuit of the present invention is different from that of FIG.

FIG. 3 is a block diagram of a video signal processing device according to a third embodiment of the present invention.

FIG. 4 is a block diagram of a conventional video signal processing device.

[Explanation of symbols]

 1 Input Terminal 2 Sync Separation Circuit 3 Control Signal Generation Circuit 4 PLL Circuit 5 A / D Converter 6 Image Memory 7 Write Control Circuit 8 Read Control Circuit 9 Processing Block (First) 10 Output Terminal 11 Output Terminal 12 Control Signal Generation Circuit (First) 13 High-speed response PLL circuit 14 Control signal generation circuit (second) 15 Low-speed response PLL circuit 16 Input terminal 17 Clock oscillation circuit 18 Clock phase shift circuit 19 Output terminal 20 Output terminal 21 Clock phase conversion circuit 22 Processing block ( 1st) 23 output terminals

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H04N 9/89 Z

Claims (5)

[Claims] 1. A first control signal generation circuit for generating a first vertical reference signal (A1) and a horizontal reference signal (A2) on the basis of a vertical synchronization signal and a horizontal synchronization signal in an input video signal, and A fast response PLL circuit that receives a horizontal reference signal (A2) as an input and generates a first clock (A3) that is phase-synchronized with a horizontal synchronizing signal in the input video signal; and the input video signal as the first clock (A3). ), An A / D converter for analog-to-digital conversion by sampling, an image memory capable of accumulating at least one field of data, the first clock (A3), the first vertical reference signal (A1), and A write control circuit for controlling writing of a data signal, which is an output signal of the A / D converter, into the image memory on the basis of a horizontal reference signal (A2);
A second frequency dividing the second clock (B3) to generate a second vertical reference signal (B1) and a read reference signal (B4)
Control signal generating circuit and the first vertical reference signal (A
1) and the second vertical reference signal (B1) are phase-compared and the band of the phase comparison signal is sufficiently narrowed to form a phase-locked loop whose response to an error variation is sufficiently slow to form the second clock ( B3) generating low speed response P
An LL circuit, a read control circuit for controlling the reading of the data stored in the image memory based on the second clock (B3) and the read reference signal (B4), and the data output from the image memory. And a processing block for processing the video signal. 2. A clock oscillating circuit in which a high-speed response PLL circuit generates a signal having a predetermined frequency, and a clock phase shift in which an output signal of the oscillating circuit is phase-shifted to generate a clock that follows fluctuations of a horizontal synchronizing signal. The video signal processing device according to claim 1, further comprising a circuit. 3. The video signal processing apparatus according to claim 1, wherein the image memory has a data rearrangement processing function. 4. A first vertical reference signal (A1) and a first vertical reference signal (A1) based on a vertical synchronization signal and a horizontal synchronization signal in an input video signal.
A first control signal generation circuit for generating the horizontal reference signal (A2), a clock oscillation circuit for generating a stable first clock (C3) having a constant frequency, and the first horizontal reference signal (A2). The first clock (C3) is used as an input to follow the fluctuation of the first horizontal reference signal (A2) and
Second clock (A) that is phase-shifted from the clock (C3) of FIG.
3) for generating a clock phase shift circuit, an A / D converter for sampling the input video signal at the second clock (A3) and performing analog-digital conversion, and the first vertical reference signal (A1). While maintaining the relative timing of the first horizontal reference signal (A2) and the first data signal (A5), which is the output signal of the A / D converter, constant from the second clock (A3) to the second A clock phase conversion circuit for converting a clock phase into one clock (C3) to generate a second vertical reference signal (C1), a second horizontal reference signal (C2) and a second data signal (C5); A first processing block for processing the second data signal (C5) output from the clock phase conversion circuit, and an image memory capable of accumulating at least one field of data and having a data rearranging function Said first clock (C3) and said second vertical reference signal (C1) and said second of said horizontal reference signal (C2) based on the second data signal (C
5) A write control circuit for controlling writing to the image memory, and a second control circuit for inputting a third clock (B3) to generate a third vertical reference signal (B1) and a read reference signal (B4). The control signal generation circuit and the first vertical reference signal (A1) and the third vertical reference signal (B1) are phase-compared with each other and the band of the phase comparison signal is sufficiently narrowed to sufficiently respond to an error variation. A low-speed response PLL circuit that forms a slow phase-locked loop to generate the third clock (B3), and stores in the image memory with the third clock (B3) and the read reference signal (B4) as references A video signal processing device comprising a read control circuit for controlling the read of the read data and a second processing block for processing the data output from the image memory. 5. The video signal processing device according to claim 1, wherein a reference signal of a control circuit for controlling the relative relationship between the recording head and the recording medium is output from the second control signal generation circuit. .