JPH03177179A - Time base collector - Google Patents

Abstract

PURPOSE:To surely and accurately extract a desired data and to attain picture reproduction without position fluctuation by replacing a video signal read from a memory into a composite synchronizing signal generated by a reference synchronizing signal generator. CONSTITUTION:When a blanking signal BLNK is fed to a switch 16, it is thrown to the position of Y to select a composite synchronizing signal CSYNC. Thus, a composite synchronizing signal CSYNC is outputted from an output terminal 12 in place of a horizontal synchronizing signal of a video signal Vout, a vertical synchronizing signal and an equalizing pulse. Thus, the composite synchronizing signal CSYNC of the video signal Vout is replaced into the composite synchronizing signal CSYNC synchronously with it and a horizontal synchronizing signal and a vertical synchronizing signal with excellent waveform in the video signal Vout obtained at the output terminal 12 are set at a correct position. Thus, the deviation in the vertical direction of a reproduced picture is prevented on the monitor screen and a desired data added in a vertical blanking period of the video signal Vout is surely and accurately extracted.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a video signal reproducing device such as a VTR (video tape recorder), and particularly relates to a time base for correcting time axis errors (jitter) of a reproduced video signal. Concerning collectors.

[Conventional technology]

During playback on a VTR, etc., fluctuations in the relative speed between the recording medium and the playback head due to distortion of the recording medium such as expansion and contraction of the magnetic tape or eccentricity of the disk cause time axis errors in the playback video signal, causing the playback image to change. Distortion and shaking occur. In order to prevent this, a time base collector can be installed in a VTR or the like to remove the time axis error component from the reproduced video signal.The time base collector has a delay means for delaying the video signal. By changing the amount of delay according to the time axis error of the reproduced video signal,
Time axis errors are removed from the reproduced video signal.

A time base collector using a line memory of several H (where IH is one horizontal period of the video signal) as a delay means is known (for example, Japanese Patent Laid-Open No. 63-228464).
Hereinafter, such a time base collector will be explained with reference to FIG. However, in the same figure, 1 is a head, 2 is an A/D (analog/digital) converter,
3 is a line memory, 4 is a D/A (digital/analog) converter, 5 is a synchronization separation circuit, and 6 is a reproduction system PLL (
7 is a reference clock generator, 8 is a frequency dividing circuit, 9 is a rotating servo circuit, 10 is a motor, 11 is a reproduction processing circuit, and 12 is an output terminal.

A signal reproduced from a recording medium (not shown) by the head 11 is supplied to the reproduction processing circuit 11, where it undergoes reproduction processing such as demodulation and filtering, and becomes a video signal.

This video signal Vin is supplied to the A/D conversion F52 and the synchronization separation circuit 5.

The synchronization separation circuit 5 separates a synchronization signal from the supplied video signal Vin, and the regeneration thread PLL 6 generates a write clock WCK and a write reset pulse WRES that are phase-synchronized with this synchronization signal. Here, the video signal Vin has a time axis error, and therefore the synchronization separation circuit 5
There is a similar time axis error in the synchronization signal outputted from the synchronous signal, and a similar time axis error is also included in the write clock WCK and write reset pulse WRES that are phase-synchronized with this.

In the A/D converter 2, the video signal Vin is the write clock W.
The signal is digitized using CK as a sampling pulse.

The obtained digital video signal is supplied to the line memory 3. The line memory 3 is internally provided with a write address counter and a read address counter.
The write address counter counts the write clock WCK and sequentially outputs write address signals of the line memory 3.

Sequential sample data of the digital video signal supplied from the A/D converter 2 is sequentially written to the address specified by the write address signal of the line memory 3.

Further, the write address counter is reset by a write reset pulse WRES. As a result, every time the write address counter is reset by the write reset pulse WRES, the start address of the line memo I73 is designated as the write address, and sequential sample data of the digital video signal is written in order from this start address. . Therefore, the cycle of the write reset pulse WRES is an integral multiple of IH in the video signal Vin, but is set to be less than or equal to the time required to write the capacity of the line memory 3. For example, if the line memory 3 has a capacity of 4H. Assuming that the period of the write reset pulse WRES is the video signal V
4H at in.

On the other hand, the reference clock generator 7 generates a read clock RCK of a constant period. The period of this read clock RCK is
It is set equal to the 1@ period of the write clock WCK when the video signal Vin has no time axis error. This read clock RCK is frequency-divided by a frequency dividing circuit 7 to generate a read reset pulse RRES and a reference vertical synchronizing signal REFV. The period of this read reset pulse RRES is the write reset pulse W when there is no time axis error in the video signal Vin.
The period of the reference vertical synchronization signal REFV is set equal to the period of the reference vertical synchronization signal REFV, and the period of the reference vertical synchronization signal REFV is also set equal to the period of the vertical synchronization signal of the video signal Vin when there is no time axis error.

In the line memory 3, while the above-mentioned read counter is reset by the read reset pulse RRES, the read clock R
CK is counted and a read address signal represented by the counted value is output. Then, sample data is read from the address specified by this read address signal. Of course, the read counter receives the read reset pulse RRES.
Each time the line memory 3 is reset, the first address of the line memory 3 is designated as the read address.

In this way, in the line memory 3, writing is performed based on the write clock WCK that includes a time axis error in the video signal Vin, and reading is performed based on the read clock RCK of a constant period, so that the digital video The time from writing to reading of each sample data of the signal (i.e., delay time) changes according to the time axis error of the video signal Vin, and therefore, a digital video signal with this time axis error corrected is output. .

This digital video signal is supplied to the D/A converter 4,
The read clock RCK is converted into an analog signal as a sampling pulse and output to the output terminal 12 as an output video signal Vout.
The signal is then supplied to a device (not shown) such as a monitor device.

The reference vertical synchronization signal REFV generated by the frequency dividing circuit 8 is supplied as a servo reference signal to the rotation system servo circuit 9, and under the control of the rotation servo circuit 9, the motor 10 rotates in synchronization with the reference vertical synchronization signal REFV. This results in
In the case of a VTR, the rotation of the head and the running of the magnetic tape are controlled based on the reference vertical synchronization signal REFV, and in the case of a disk playback device such as a video disk device, the rotation of the disk is controlled based on the reference vertical synchronization signal REFV. rotation is controlled. As a result, even if there is a time axis error in the reproduced video signal, its vertical synchronization frequency and horizontal synchronization frequency will on average match the frequency of the reference vertical synchronization signal REFV and the reference horizontal synchronization signal corresponding thereto, and these Steady frequency deviation is eliminated. In the line memory 3, the time axis error remaining after excluding the steady deviation of the synchronization frequency from the time axis error is removed from the video signal Vin.

[Problem to be solved by the invention]

Incidentally, in the time base collector, similar delay processing is performed on the synchronization signal of the video signal. For this reason, if the edges of the synchronization signal of the video signal input to the time base collector are dull or the synchronization signal is missing, this signal is output as is from the time base collector. To prevent this, when a frame memory or field memory is used as a delay means in the timebase collector, the synchronization signal generated from the reference clock is replaced with the synchronization signal of the video signal output from the memory of the timebase collector. That's what I do. This synchronizes the frame memory and field memory read reset pulses with the horizontal and vertical synchronization signals generated from the reference clock, and synchronizes the synchronization signals of the video signal output from the memory with these horizontal and vertical synchronization signals. This is because it is possible.

On the other hand, when a line memory is used as the delay means of the time base collector as in the above conventional technology, the video signal output from the line memory, especially the vertical synchronization signal, is synchronized with the vertical synchronization signal generated from the reference clock. Therefore, the above synchronization signal cannot be replaced. This point will be explained below using FIG. 6.

FIG. 6(A) is the reference vertical synchronization signal REF in FIG.
In contrast, as shown in FIG. 6(B),
The playback processing circuit 11 receives the playback video signal Vin whose vertical synchronization frequency is on average equal to the frequency of the reference vertical synchronization signal REFV.
is obtained, digitized, and written and read in the line memory 3. At this time, the periods of the write reset pulse WRES and read reset pulse RRES of the line memory 3 are respectively 4H in the above sense. If so, as shown in FIG. 6(C), the phase is synchronized with the horizontal synchronizing signal in the reproduced video signal Vin (FIG. 6(B)) every 4H, and the phase is synchronized with the horizontal synchronizing signal in FIG. ) (This (a) is the read reset pulse RRES (b) when the phase is shown in FIG. 6(F).)
) is the video signal V at the output terminal 12
horizontal synchronization signal of out(a) (Figure 6(E)) and 4H
The phase is synchronized for each.

Here, read reset pulse RRE shown in FIG. 6(D)
S(a) has a phase difference ΔΦ with respect to the write reset pulse WRES (FIG. 6(C)), and this phase difference ΔΦ changes depending on the time axis error. Therefore, a phase difference of ΔΦ occurs between the vertical synchronizing signal of the output video signal Vout(a) (FIG. 6(E)) and the reference vertical synchronizing signal REFV (FIG. 6(A)).

On the other hand, write reset pulse WRES (Figure 6(C))
The phase relationship of the read reset pulse RRES with respect to the frequency dividing circuit 8 is determined by the reset timing of the frequency dividing circuit 8, and is arbitrary. Therefore, as shown in FIG. 6(F), the read reset pulse RRES (b) is changed to the write reset pulse WRES (
If the phase is shifted by ΔΦ′ which is different from ΔΦ with respect to FIG. 6(C)), the output video signal Vout at this time is
The vertical synchronization signal in (b) is the reference vertical synchronization signal REF.
A phase difference of ΔΦ', which is different from ΔΦ, is generated between V (FIG. 6(A)).

In this way, the phase of the vertical synchronization signal of the output video signal Vout with respect to the reference vertical synchronization signal REFV changes depending on the phase difference between the write reset pulse WRES and the read reset pulse RRES, and the frequency dividing circuit 8 Figure 6 (
If a composite synchronization signal C3YNC as shown in H) is generated and replaced with the composite synchronization signal of the output video signal Vin,
Even if the horizontal synchronization signal is correctly replaced within that horizontal blanking period, the vertical synchronization signal and equalization pulse will not be set to the correct positions during that vertical blanking period, and these set positions will be the same as the write reset pulse WRES. It changes depending on the phase difference between the read reset pulse RRES and the read reset pulse RRES.

The reason for the positional shift of the vertical synchronization signal when replacing the composite synchronization signal with the output video signal Vout is the write reset pulse WRES and read reset pulse RR.
In addition to the fact that the phase with the ES is not constant, there is another reason why the position of the vertical synchronization signal in the output video signal Vout cannot be set correctly due to replacement of the composite synchronization signal.

That is, in the case of a VTR, the recording position of the vertical synchronization signal on the magnetic tape is set at one end of the track on the magnetic tape, but some variation in this recording position is allowed. However, this tolerance is quite large (for example, ±3H in the case of the VH5 standard), and as a result, even for each VTR, there are variations in the recording position of the vertical synchronizing signal on the magnetic tape. Even if the head 1 is rotated in synchronization with the reference vertical synchronization signal REFV generated in 8, the vertical synchronization signal of the reproduced video signal Vin cannot be compared to the reference vertical synchronization signal for any magnetic tape recorded on any VTR. It is not possible to maintain a constant phase relationship.

The phase shift of the vertical synchronization signal of this reproduced video signal Vin with respect to the reference vertical synchronization signal REFV is the output video signal Vout.
Therefore, if the composite synchronization signal of the output video signal Vout is replaced with a composite synchronization signal that has a predetermined phase relationship with the reference vertical synchronization signal REFV, the position of the vertical synchronization signal can be set correctly within the vertical blanking period. It will not be done.

As described above, if the position of the vertical synchronization signal is not set correctly within the vertical blanking period of the output video signal Vout, the entire image on the screen of the monitor device will be shifted in the vertical direction. However, in the case of a video signal such as teletext broadcasting where data with meaningful content is added at a predetermined position in the vertical blanking period, it becomes a standard for forming a gate signal to extract this data. Since the position of the vertical synchronization signal is shifted, this data cannot be extracted satisfactorily.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a time base collector using a line memory, which eliminates such problems and prevents displacement of vertical synchronization signals due to replacement of synchronization signals.

[Problem to be solved by the invention]

In order to achieve the above object, the present invention provides first means for obtaining synchronization information that is phase-synchronized with a vertical synchronization signal of a video signal read out from a line memory; and third means for replacing the composite synchronization signal with the composite synchronization signal of the video signal read from the line memory.

[For production]

Since the synchronization information obtained by the first means is phase-synchronized with the vertical synchronization signal of the output video signal of the line memory,
The vertical synchronization signal of the composite synchronization signal generated by the second means is also phase-synchronized with the vertical synchronization signal of the output video signal of the line memory. Therefore, even if the composite synchronization signal of the output video signal of the line memory is replaced with the composite synchronization signal generated by the second means, the resulting video signal will have the following:
At a predetermined position within the vertical blanking period, without any positional deviation.
The vertical synchronization signal will be positioned.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a time base collector according to the present invention, in which 13 is a synchronization separation circuit, 14
1 is a reset pulse generation circuit, 15 is a reference synchronization signal generator, and 16 is a switch. Parts corresponding to those in FIG. 5 are denoted by the same reference numerals, and redundant explanation will be omitted.

In the same figure, a video signal Vo whose time base error has been corrected in the same manner as the conventional time base collector shown in FIG.
ut is output from the D/A converter 4, passes through the switch 16 which is normally closed to the X side, and is output from the output terminal 12.

Further, this video signal Vout is supplied to the synchronization separation circuit 13 to separate the synchronization signal, and a reset pulse 5RES synchronized with the vertical synchronization signal is sent to the reset pulse generation circuit 13.
Generated in 4. The reference synchronization signal generator 15 generates a composite synchronization signal C3YNC and a blanking signal BLNK in synchronization with this reset pulse 5RES. This composite synchronization signal C3YNC is synchronized with the composite synchronization signal in the video signal Vout, and is supplied to the Y side of the switch 16. The blanking signal BLNK also synchronizes the video signal Vou with the composite synchronization signal inside, and the horizontal synchronization signal period of the horizontal blanking period in this video signal Vout and the period including the vertical synchronization signal and the equalization pulse. It represents.

The switch 16 is normally closed to the X side, but when the blanking signal BLNK is supplied, it is closed to the Y side and selects the composite synchronization signal C3YNC. As a result, the video signal Vo
A composite synchronization signal C5YNC is output from the output terminal 12 instead of the horizontal synchronization signal, vertical synchronization signal, and equalization pulse of ut.

In this way, this video signal Vout t has its composite synchronization signal replaced with the composite synchronization signal csyNC synchronized therewith, and the video signal Vout obtained at the output terminal 12 has horizontal and vertical synchronization signals with good waveforms. is set to the correct position. Therefore, it is not only possible to prevent the reproduced image from shifting in the vertical direction on the monitor screen, but also to reliably and accurately extract the desired data added during the vertical blanking period of the video signal Vout.

FIG. 2 is a block diagram showing another embodiment of the time base collector according to the present invention, in which 17 is a flag data generation circuit, 18 is a switch, and 19 is a flag data detection circuit, parts corresponding to those in FIG. are given the same reference numerals and redundant explanations will be omitted.

In the figure, a switch 18 is provided between the A/D converter 2 and the line memory 3. A digital video signal output from the A/D converter 2 is supplied to the P side of this switch 18, and flag data output from the flag data generation circuit 17 is supplied to the Q side. This flag data is A
/D converter 2 cannot generate the data.

The switch 18 is normally closed to the P side, and the digital video signal output from the A/D converter 2 is supplied to the line memory 3. Then, when the vertical synchronization signal PBVD of the video signal Vin is output from the synchronization separation circuit 5, the switch 18 is closed to the Q side using this as a control signal, and the flag data output from the flag data generation circuit 17 is supplied to the line memory 3. be done.

That is, the digital video signal output from the A/D converter 2 is written into the line memory 3 with its vertical synchronization signal period replaced with flag data.

The digital video signal output from line memory 3 is
The flag data is supplied to the D/A converter 4 and converted into analog data, and is also supplied to the flag data detection circuit 19 to detect flag data, and the reset pulse 5RES is generated by the reset pulse generation circuit 14 based on this flag data.

Hereinafter, 'W, as in the embodiment shown in FIG.
The switch 16 is controlled by K and the video signal Vou
The composite synchronization signal of t is replaced with the composite synchronization signal C3YNC.

As described above, this embodiment also provides the same effects as the embodiment shown in FIG. Since it can be made into an IC and embedded in the IC of another digital circuit, the area occupied by these on the board can be reduced to virtually zero, so compared to the embodiment shown in FIG. The scale will be reduced.

FIG. 3 is a block diagram showing still another embodiment of the time base collector according to the present invention, in which 20 is a phase difference detection circuit, 21 is a phase shift circuit, and parts corresponding to those in FIG. 1 are denoted by the same reference numerals. and omit duplicate explanations.

In the figure, the phase difference ΔΦ between the write reset pulse WRES output from the reproduction system PLL 6 and the read reset pulse RRES output from the frequency dividing circuit 8 is detected by the phase difference detection circuit 20, and the phase difference ΔΦ is detected according to this phase difference ΔΦ. The shift amount of the phase shift circuit 21 is set. The vertical synchronization signal PBVD separated by the synchronization separation circuit 5 is converted to Δ by the phase shift circuit 21.
The phase is shifted by Φ and supplied to the reset pulse generation circuit 14 to generate the reset pulse 5RES. In synchronization with this reset pulse 5RES, a composite synchronization signal C3YNC and a blanking signal B are output from the reference synchronization signal generator 15.
LNK is output.

As explained in FIG. 6, the video signal Vin is delayed by the phase difference ΔΦ between the write reset pulse WRES and the read reset pulse RRES in the line memory 3, and the output video signal V
It becomes out. Therefore, the video signals Vin, Vo
There is a phase difference of ΔΦ in the vertical synchronization signal of ut. Therefore,
The vertical synchronization signal PBVD, which is separated from the video signal Vin by the synchronization separation circuit 5 and phase-shifted by ΔΦ by the phase shift circuit 21, is phase-synchronized with the vertical synchronization signal of the output video signal Vout, and therefore, the reference synchronization signal is generated. vessel 15
The composite synchronization signal C3YNC output by the output video signal Vo
This means that it is in phase synchronization with the composite synchronization signal of ut.

In this way, also in this embodiment, the composite synchronization signal can be replaced without positional deviation of the vertical synchronization signal, and the same effect as the embodiment shown in FIG. 1 can be obtained.

FIG. 4 is a block diagram showing still another embodiment of the time base collector according to the present invention, and 22 is a reference system P.
L L, 23.24 is a switch, 25 is a decoding circuit, 26 is an A/D converter, 27 is a line memory, 28 is a D
/A converter, 29 is an encode circuit, 30 is an output terminal,
31 is an adder, 32 is an output terminal, and 33 is an input terminal. Portions corresponding to those in FIG. 1 are given the same reference numerals and redundant explanations will be omitted.

In this embodiment, the reproduced luminance signal and carrier color signal are processed separately, and synchronized operation with an external device is possible.

In FIG. 4, the reproduction processing circuit 11 separately outputs the reproduced luminance signal Yin and the carrier color signal Cin. This luminance signal Yin is the reproduced video signal Vi in FIG.
Similarly to n, it is digitized by the A/D converter 2, written to and read out from the line memory 3, and then digitized by the D/A converter 4.
The luminance signal Yout is converted into an analog signal by the switch 16 and replaced by the composite synchronization signal C3YNC from the reference synchronization signal generator 15.

On the other hand, the carrier color signal Ci output from the reproduction processing circuit 11
n is supplied to the decoding circuit 25, and two color difference signals R-
It is demodulated into Y and B-Y. These color difference signals R-Y, B-
Y is supplied to the A/D converter 26 and digitized using the write clock WCK' generated by the reproduction system PLL 6 as a sampling pulse.

The digital color difference signal outputted from the A/D converter 26 is supplied to the line memory 27, and similarly to the line memory 3, the write clock WCK' generated by the reproduction system PLL 6,
The read clock RCK' is written by the write reset pulse WRES'' and is read out by the read clock RCK' generated by the reference system PLL 22, and the read reset pulse RRES'.Thereby, the time axis error included in the digital color difference signal is corrected.

The digital color difference signal read out from the line memory 27 is supplied to the D/A converter 28, and the readout clock RCK'
is converted into an analog signal as a sampling pulse, and two color difference signals R-Y%B-Y are obtained. These color difference signals R-
Y and B-Y are supplied to an encoding circuit 29, which performs quadrature two-phase modulation on the color subcarrier SC supplied from the reference synchronization signal generator 15 to generate a carrier color signal Cout.

Here, the line memory 3.27 operates so that no delay difference occurs between the luminance signal You t and the carrier color signal Cout, and the luminance signal You t is transmitted from the output terminal 12 to the carrier color signal Cout. are respectively output from the output terminal 30, and these luminance signal Yout and carrier color signal C
out is added by an adder 31 and outputted from an output terminal 32 as a composite color video signal Vout.

Note that the A/D converter 26 receives two color difference signals R-YS.
B-Y is multiplexed and digitized, and the D/A converter 2
8, the digital color difference signal read out from the line memory 27 is converted into analog and separated into color difference signals R-Y and B-Y.
A D converter, a line memory, and a D/A converter may be provided and the time axis error may be corrected separately.

Furthermore, since the color difference signals R-Y and B-Y have a narrow band compared to the luminance signal Yin, the write clock WCK' and the read clock RCK'' are set to clocks with a lower frequency than the write clock WCK and the read clock RCK, respectively. Accordingly, the capacity of the line memory 27 can be made smaller than the capacity of the line memory 3.

This embodiment is further configured to allow selection between free operation, which operates independently of an external device (not shown), and external synchronized operation, which operates in synchronization with the external device.

In the case of free operation, the control signal INT/EXT
Switch 23 is turned on and switch 24 is closed to the S side.

Thereby, the reference clock output from the reference clock generator 7 is supplied to the reference system PLL 22. In this case, the reference system PLL 22 divides the reference clock from the reference clock generator 7 and generates the read clocks RCK, RCK' and the read reset pulses RRES, RRES, similarly to the frequency dividing circuit in FIGS. 1 to 3. ”, reference vertical synchronization signal REF
Generate V.

Thereby, the embodiment operates in the same manner as the embodiment shown in FIG. 1, and the same effects can be obtained.

In addition, in the case of externally synchronized operation, the control signal INT/EX
T turns off the switch 23 and closes the switch 24 to the T side. An external synchronization signal ESYNC from an external device is input to the input terminal 33, and in synchronization with this, the reference system PLL
22 works. As a result, the reference system PLL 22 outputs a reset pulse 5RES that is phase-synchronized with the vertical synchronization signal of the external synchronization signal ESYNC, and is supplied to the reference synchronization signal generator 15 via the switch 24. Therefore, the composite synchronization signal of the luminance signal Yout output from the switch 16 is the external synchronization signal ESYN from the input terminal 33.
It will be synchronized with C.

In this way, in the case of externally synchronized operation, by replacing the luminance signal read from the line memory 3 with the composite synchronization signal, a video signal synchronized with the external device can be obtained.

In the case of externally synchronized operation, the luminance signal output from the D/A converter 4 is synchronized with the phase of the read reset pulses RRES and RRES' output from the reference system PLL 22 with the horizontal synchronization signal of the external synchronization signal ESYNC. Yo
The phase of the horizontal synchronization signal of ut can be synchronized with the horizontal synchronization signal of the composite synchronization signal C3YNC output from the reference synchronization signal generator 15. On the other hand, this luminance signal Y
The phase relationship between the out vertical synchronization signal and the composite synchronization signal C3YNC is the external synchronization signal ESYNC and the reproduced luminance signal Yi.
The phase relationship with the vertical synchronization signal of n and the write reset pulse W
Since it is determined by the phase relationship between RES and read reset pulse RRES, it is extremely difficult to always synchronize the vertical synchronization signal of the luminance signal Yout with the vertical synchronization signal of the composite synchronization signal C3YNC.

However, by making the reference vertical synchronization signal REFV output from the reference system PLL 22 always have a predetermined phase relationship with the vertical synchronization signal of the external synchronization signal ESYNC, it is possible to combine the reference vertical synchronization signal REFV with the vertical synchronization signal of the luminance signal Yout The phase shift between the synchronization signal C3YNC and the vertical synchronization signal can be kept within a few H. Therefore, acceptable image reproduction is possible even if the reproduced image is displayed vertically with a shift of about a few H on the monitor screen. becomes.

Although the present invention has been described in detail above, the present invention is not limited only to these examples.

That is, the numerical values listed above are shown for convenience of explanation, and can be any numerical value. For example, the capacity of line memory 3 is set to 4H, which is N if N is a positive integer.
It can be H.

In addition, the video signal whose time axis error has been corrected is transferred to switch 1.
Although the composite synchronization signal was replaced by switching 6,
After a blanking signal is added to this video signal in either an analog or digital state, a composite synchronization signal may be added and replaced.

Furthermore, in the embodiments shown in FIGS. 1 to 3, it is also possible to selectively perform free operation and externally synchronized operation in the same manner as in the embodiment shown in FIG.

〔Effect of the invention〕

As explained above, according to the present invention, in a time base collector using a memory with a capacity of line units, the video signal read from the memory can be combined without any positional shift in the vertical synchronization signal. The synchronization signal can be replaced with a good composite synchronization signal generated by the reference synchronization signal generator, and there is no distortion or shaking caused by time axis fluctuations on the monitor screen, and there is no vertical shift caused by positional deviation of the vertical synchronization signal. Not only is it possible to reproduce images without positional fluctuations, but
It becomes possible to reliably and accurately extract desired data added at fixed positions during the vertical blanking period.

Furthermore, the present invention can synchronize the operation of an external device with a video signal whose time axis error has been corrected.

[Brief explanation of drawings]

1 to 4 are block diagrams showing embodiments of a time base collector according to the present invention, FIG. 5 is a block diagram showing an example of a conventional time base collector, and FIG. 6 is an explanatory diagram of its operation. . 2...A/D converter, 3...line memory, 4...
・D/A converter, 5... Synchronization separation circuit, 6... Reproduction system PLL, ? ... Reference clock generator, 8... Frequency dividing circuit, 12... Output terminal, 13... Synchronization separation circuit,
15... Reference synchronization signal generator, 16... Switch,
17... Flag data generation circuit, 18... Switch, 19... Flag data detection circuit, 20... Phase difference detection circuit, 21... Phase shift circuit, 22... Reference system P L L , 23.24...switch, 33...
・Input terminal for external synchronization signal. (H)C5YNC Figure 6

Claims (1)

[Claims] 1. A memory having a capacity in units of lines is provided, an input video signal having a time axis error is written into the memory using a write clock synchronized with the input video signal, and a read clock having a constant cycle is provided. In the time base collector, the time base collector obtains a video signal whose time axis error has been corrected by reading the video signal from the memory, the first step is to obtain synchronization information that is phase-synchronized with the vertical synchronization signal of the video signal read from the memory. means for generating a composite synchronization signal in which a vertical synchronization signal is phase-synchronized with the synchronization information; and a composite synchronization signal of the video signal read from the memory, generated by the second means. a third signal that replaces the composite synchronization signal;
A time base collector characterized by having means for and. 2. In claim 1, the first means is means for separating a vertical synchronization signal of the video signal read from the memory, and the vertical synchronization signal is used as the synchronization information. Timebase collector. 3. In claim 1, there is provided means for replacing the vertical synchronization signal of the input video signal with a flag signal of specific information content, and the first means replaces the flag signal of the video signal read from the memory. A time base collector, characterized in that the time base collector is means for extracting the flag signal, and uses the flag signal as the synchronization information. 4. In claim 1, the first means includes a fourth means for detecting a delay amount of the video signal caused by the memory, and a phase shift amount is set equal to the detected delay amount of the input video signal. a fifth means for phase-shifting a vertical synchronization signal separated from the time base collector, the time base collector comprising: a fifth means for phase-shifting a vertical synchronization signal separated from the time base collector, and using the phase-shifted vertical synchronization signal as the synchronization information. 5. In claim 4, the fourth means is means for detecting a phase difference between a write reset pulse and a read reset pulse of the memory, and the phase difference is the delay amount. timebase collector. 6. In claim 1, 2, 3, 4 or 5, the read pulse generating means for generating the read clock and read reset pulse of the memory receives a reference clock or an external synchronization signal from an external device, and the external synchronization signal When inputting, the read pulse generating means generates the synchronization information phase-synchronized with the vertical synchronization signal of the external synchronization signal, and supplies the synchronization information to the second means in place of the synchronization information by the first means. Features a time base collector.