JPH03186084A - Video signal reproducing device - Google Patents

Abstract

PURPOSE:To prevent the occurrence of a time lag between a reproduced video signal and a dropout pulse by applying the same time axis compensation as that for a reproduced video signal to the dropout pulse. CONSTITUTION:The time axis fluctuation of a reproduced video signal is eliminated by a 1st TBC 10 and a write clock synchronously with the reproduced video signal is generated to the TBC 10 and a TBC controller 12 forming a stable readout clock is provided. Moreover, a memory supplying a dropout pulse is provided and a 2nd TBC 11 is provided, in which a TBC controller 12 in common use with the 1st TBC 10 controls the memory. Then a circuit 15 compensating the dropout with the dropout pulse from the TBC 11 is provided to the output side of the TBC 12. Thus, the occurrence of a time lag between the video signal and the dropout pulse is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal reproducing device applied to a rotary head type VTR.

(Summary of the Invention) This invention consists of a memory and a controller that controls writing and reading of the memory, writes a reproduced signal into the memory with a clock synchronized with the reproduced signal reproduced by a magnetic head, and writes the reproduced signal with a stable clock. a first TBC that reads out the data from the memory, a second TBC that has a memory that is supplied with a dropout pulse detected from the reproduction signal and whose memory is controlled by the controller of the first TBC; A dropout compensation circuit is provided on the output side of the second TBC and is controlled by the dropout pulse output from the second TBC, thereby preventing the occurrence of a time lag between the dropout pulse and the reproduced video signal. can.

[Conventional technology]

A rotating head type VTR is known in which a pair of magnetic heads are attached to a tape guide drum that rotates at a frame frequency, and the magnetic heads alternately contact a magnetic tape that is wound obliquely around the circumferential surface of the guide drum. This type of VTR detects as a dropout when the level of the reproduced signal from the magnetic head becomes lower than a specified value, and uses a dropout compensation circuit using an IH delay line to compensate for the dropout period using the previous reproduced signal. Was.

[Problem to be solved by the invention]

It is effective to provide a digital TBC in order to improve the quality of images reproduced by a VTR. In other words, by writing the reproduced luminance signal into the memory using a write clock synchronized with the reproduced luminance signal and reading the reproduced luminance signal from the memory using a stable read clock, it is possible to remove time axis fluctuations called jitter. When performing dropout compensation on the output side of the TBC, there is a problem in that a time lag occurs between the time axis compensated luminance signal and the dropout pulse.

Therefore, an object of the present invention is to provide a video signal reproducing device that can prevent a time lag from occurring between a reproduced video signal and a dropout pulse when performing dropout compensation on the output side of a TBC. It is in.

[Means to solve the problem]

This invention consists of a memory (40) and a controller (engineering part 2) that controls writing and reading of the memory (40), and supplies a reproduced signal to the memory (40) with a clock synchronized with the reproduced signal reproduced by a magnetic head. It has a first TBC (10) for writing and reading a reproduced signal from the memory (40) using a stable clock, and a memory (46) to which a dropout pulse detected from the reproduced signal is supplied, and the memory (46) 1st T
The second controller controlled by the controller (12) of the BC (10)
TBC (11), and a dropout compensation circuit (15) provided on the output side of the first TBC (10) and controlled by a dropout pulse output from the second TBC (11). Consisting of

[Effect]

The time axis variation of the reproduced video signal is removed by the first TBCIO. The TBCIO is provided with a TBC controller 12 that generates a write clock synchronized with the reproduced video signal and forms a stable read clock. A second TBC is provided with a memory 46 supplied with dropout pulses, the memory 46 being controlled by a common TBC controller 12 with the first TBCIO.
ll is provided. On the output side of TBCIO, TBC
Since the circuit 15 for compensating for dropout using the dropout pulse from II is provided, it is possible to prevent a time lag from occurring between the video signal and the dropout pulse.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. This description will be made according to the following order.

a. Overall configuration TBC c. Control of TBC operation a. Overall configuration In FIG. 1, l is the input terminal for the FM modulated luminance signal separated from the reproduced signal. The limiter 2, the FM demodulation circuit 3, and the de-emphasis circuit 4 demodulate the FM modulation degree signal. The reproduced luminance signal from the de-emphasis circuit 4 is supplied to the mixer 5, and the pseudo vertical synchronizing signal QVD is inserted in the mixer 5 only during variable speed reproduction.

A switching pulse Ps is supplied from a terminal 7 to the pseudo vertical synchronization signal generation circuit 6 . switching pulse Ps
is a pulse signal that is inverted for each field in synchronization with the rotational phase of the tape guide drum, that is, the magnetic head.

The switching pulse Ps is formed from the output signal of a magnetic rotation detector associated with the tape guide drum. The pseudo vertical synchronization signal generation circuit 6 generates a pseudo vertical synchronization signal QVD whose timing is delayed by a predetermined time from the rising edge and the falling edge of the switching pulse Ps. The pseudo vertical synchronization signal QVD is supplied to the mixer 5 via the gate circuit 8.

The gate circuit 8 is supplied with a control signal from a terminal 9 indicating that variable speed reproduction is in progress. Variable speed playback operations include slow playback, still playback, cue playback, review playback, and the like. Therefore, the pseudo vertical synchronization signal Q is supplied to the mixer 5 via the gate circuit 8 only during these variable speed playback operations.
VD is supplied.

During variable speed playback, the level of the playback signal fluctuates greatly and the level of the vertical synchronization signal becomes small (if this happens, the vertical synchronization of the monitor may become unstable).

For this reason, a pseudo vertical synchronization signal QVD is inserted during gear shifting.

The output signal of the mixer 5 is supplied to the TBCIO and TBC controller 12. TBCII regarding color signals is also provided. A low frequency conversion color signal is supplied to this TBCII from an input terminal 13. A write timing signal and a read timing signal are commonly supplied to the TBCIO and 11 from the TBC controller 12.

For example, TBCIO and 11 have an FI with a capacity of 5 lines.
An FO memory is provided respectively. A luminance signal and a low frequency conversion color signal digitized at a sampling frequency of 4fse (fsc: color subcarrier frequency) are written into this memory. The write-side clock is generated by a PLL based on a horizontal synchronization signal separated from the reproduced luminance signal.

The read-side clock is formed based on the output signal of the crystal oscillator 14. Signals read from the TBCIO and 11 memories are converted into analog signals by the D/A converters, respectively.

The time-base compensated luminance signal from TBCIO is supplied to the noise removal and dropout compensation circuit 15. Dropout is detected from the level of the reproduced signal, and a dropout pulse with a pulse width corresponding to the dropout period is generated. As will be described later, this dropout pulse is subjected to the same time axis compensation as the luminance signal and the low frequency converted color signal, for example, using TBCII for the color signal. This time-base compensated dropout pulse is supplied to the noise removal and dropout compensation circuit 15.

Regarding the luminance signal, noise is removed using a cyclic comb filter. Since this noise removal degrades the resolution in the vertical direction, it operates only when the tape speed during reproduction is slow and the S/N of the reproduced luminance signal is poor. Also, I
The noise removal and dropout compensation circuit 15 is provided with a correlation detector that generates a detection signal indicating the presence or absence of vertical correlation from the level of the difference signal between the delayed H (H: horizontal period) signal and the non-delayed signal. . This detection signal is supplied to a noise removal circuit 21 regarding color signals. Furthermore, the IH delay circuit required for dropout compensation is also used as a noise removal and correlation detector. A reproduced luminance signal from the noise removal and dropout compensation circuit 15 is taken out to an output terminal 16 and is also supplied to a mixer 17. A composite color video signal is taken out at the output terminal 18 of the mixer 17.

The low-pass converted color signal from TBCII is supplied to the frequency converter 20. In the frequency converter 20, the low-pass converted color signal is converted to the original carrier frequency fse (in the NTSC system, fsc=
0 frequency converter 20 which converts the signal back to 3.58MHz)
A carrier color signal is supplied to the noise removal circuit 21.

The noise removal circuit 21 is provided with a crosstalk removal circuit, a noise removal circuit using a cyclic comb filter, a contour compensation circuit, etc. in the same way as for the luminance signal.

The above-mentioned detection signal obtained from the reproduced luminance signal is supplied to the noise removal circuit 21 regarding the carrier color signal, and the vertical direction non-correlation section stops vertical noise removal.
Vertical color degradation is prevented. The reproduced color signal from the noise removal circuit 2i is taken out to the output terminal 19 and is also supplied to the electric mixer 17. Output terminals 16 and 1
9, a luminance signal and a carrier color signal are obtained, respectively.

As described above, when the correlation detection signal generated by the noise removal and dropout compensation circuit 15 is supplied to the noise removal circuit 21, in order to prevent the occurrence of a time lag between the color signal and this detection signal, the TBCII A noise removal and dropout compensation circuit 15 is provided on the output side of the circuit.

b, TBC FIG. 2 shows a more detailed configuration of the TBCIO and I L TBC controller 12. 5Y is an input terminal to which the luminance signal from the mixer 5 is supplied, and 13 is the input terminal to which the low frequency conversion color signal is supplied. 31 is an input terminal to which a dropout pulse DOP is supplied. The dropout pulse DOP can be formed by supplying the FM modulated luminance signal to a limiter and performing envelope detection on the output signal of the ivy. During the dropout period when the envelope of the FM modulated luminance signal is below a predetermined level, the dropout pulse DOP becomes, for example, a high level.

The luminance signal is sent to the clamp circuit 32 of TBCIO and TBC.
The signal is supplied to the synchronous separation circuit 33 of the controller 12. The horizontal synchronization signal separated by the synchronization separation circuit 33 is
34. The PLL 34 generates a signal with a horizontal frequency synchronized with the reproduced luminance signal and a clock with a frequency of 4 fsc. These signals are supplied to the timing generation circuit 35. The output signal of the crystal oscillator 14 is also supplied to the timing generation circuit 35.

Further, the output signal of the crystal oscillator 14 is supplied to a frequency divider 36, and the output signal of the frequency divider 36 is supplied to a drum servo circuit 37. As will be described later, the drum servo circuit 37 consists of a phase servo circuit and a speed servo circuit, and the output signal of the 0 frequency divider 36 that controls the rotational operation of the drum motor 38 is used as a servo reference signal for the phase servo circuit. be done.

By frequency-dividing the clocks on the read side of TBCIO and 11 and supplying them to the drum servo circuit 3v, the TBCI
The frequencies of the write clocks of O and 11 and their read clocks can be made to match on average. As a result, overtaking can be prevented from occurring between the write address and the read address.

An A/D converter 39 is connected to the output side of the clamp circuit 32, and a write clock WCK is supplied from the timing generation circuit 35 to the A/D converter 39.

The sampling frequency from the A/D converter 39 is 4 fs.
At c, a digital luminance signal of 8 bits per sample is generated. This digital luminance signal is stored in the buffer memory 40.
is input. The buffer memory 40 is supplied with a write clock WCK and a reset write pulse WRES from the timing generation circuit 35. These write side signals WCK and WRES are formed from the output signal of the PLL 34.

A timing generation circuit 35 supplies a read clock RCK and a reset read pulse RRY generated from a stable output signal of the crystal oscillator 14 to a buffer memory 40.
A digital luminance signal from which time axis fluctuations have been removed is obtained from the buffer memory 40. This digital luminance signal is D
/A converter 41 converts the signal into an analog signal. A low-pass filter 42 is connected to the D/A converter 41, and a reproduced luminance signal from which time axis fluctuations have been removed is extracted from an output terminal 43 of the low-pass filter 42.

Similarly to the luminance signal, a clamp circuit 44, an A/D converter 45, a buffer memory 46, a D/A converter 47, and a low-pass filter 48 are provided for the low-frequency converted color signal from the input terminal 13.

The output terminal 49 outputs a low frequency converted color signal from which time axis fluctuations have been removed. The writing side of the buffer memory 46 is controlled in the same way as the luminance signal, but the reading side is controlled by a read clock RCK and a reset read pulse RRC.

The sampling frequency from the A/D converter 45 is 4 fsc.
A digital signal of 6 bits per sample is obtained. Like the buffer memory 40, the buffer memory 46 has a capacity to store 8-bit data for 5H.In the case of a 0 color signal, the number of quantization bits is 2 bits less than that of a luminance signal. , an unused memory area is created in the buffer memory 46. This memory area is allocated to the dropout pulse DOP (1 bit) from the input terminal 31. Therefore, the dropout pulse DOP from the buffer memo 146 has time axis fluctuations removed in the same way as the luminance signal and the low frequency conversion color signal. This dropout pulse D.

P is taken out to the output terminal 51 via the IH delay circuit 50.

In this example, the dropout pulse D.

Since time axis compensation is performed for P using the buffer memory 46, memory capacity can be saved.

As mentioned above, the noise removal and dropout compensation circuit 15 is provided on the output side of the TBCIO, and this circuit 1
5 is supplied with a dropout pulse DOP from TBCII. The dropout period during which the dropout pulse DOP is at a high level is compensated by the brightness signal before IH. Since the reproduced luminance signal and the dropout pulse DOP are subject to the same control in the time axis direction, the dropout compensation circuit does not cause a time difference between the two.

The buffer memory 40 is composed of a 5H FIFO memory. Writing and reading from the FIFO memory can be performed independently and asynchronously in different cycles. FIG. 3 shows the configuration of an example of the buffer memory 40,
The memory array shown at 52 has a capacity of (8 bits x 5048 words). In the case of the NTSC system, when the sampling frequency is 4fsc, the data for 5H is (910×5−4550 words).

8-bit data is supplied to the memory array 52 via a manual buffer 53, and output data from the memory array 52 is taken out via an output buffer 54. The input buffer 53 is controlled by write enable WE, and the output buffer 54 is controlled by read enable RE.

A write address pointer generation circuit 55 is provided to determine the write position in the memory array 52. A read address pointer generation circuit 56 is provided to determine the read position of the memory array 52. The write address pointer generation circuit 55 is supplied with a write clock WCK and a reset write pulse WRES. The reset write pulse WRES returns the pointer to the initial position (0
address), and the position of the pointer is incremented by the write clock WCK. Similarly, the read address pointer is controlled.

The buffer memory 46 also has the same configuration as the buffer memory 40 described above, and RRC is used as a reset read pulse.
Supplied in place of RYO.

FIG. 4 shows signals supplied from the timing generation circuit 35 to the buffer memories 40 and 46.

The reset read pulse RPC is delayed by 2H with respect to the reset write pulse WRES, and RRY is I with respect to RRC.
H is late. These pulses WRES, RRC,,R
RY has a period of 5H.

The time difference between the reset write pulse WRES and the reset read pulse RRCSRRY changes according to the time axis fluctuation of the reproduced signal. 0 When there is no time axis fluctuation, a 2H delay is applied to the input side. The signal is TBC
A luminance signal obtained from II and given a delay of 3H to the input terminal is obtained.

The relationship between the color signal and luminance signal on the output side of the TBC is as follows:
The chrominance signal is IH1 ahead of the luminance signal. By controlling the readout timings of TBCIO and 11 in this manner and creating a time difference between the luminance signal and the low-frequency conversion color signal, the noise removal circuit 21 at the subsequent stage of the TBC
It is possible to compensate for the color signal delay that occurs in That is, the noise removal circuit 21 is provided with a crosstalk removal circuit, and passing through this crosstalk removal circuit causes an IH delay in the color signal. IH delay occurs in the case of a crosstalk removal circuit using an IH delay line or a crosstalk removal circuit using a 3-line logical comb filter. A logical filter is a filter that extracts multiple points in a waveform to determine the shape of signal change, and can remove crosstalk 4 without causing vertical blur.

Further, the IH delay circuit 50 to which the dropout pulse DOP outputted from the buffer memory 46 of the TBCII is supplied has the dropout pulse DOP leading by IH with respect to the luminance signal at the same time as the low frequency conversion color signal. There are stings provided to compensate for that.

Of course, it is possible to compensate for not only the time difference between IH but also the time difference between the luminance No. 13 and the color signal caused by a filter or the like provided in the No. 43 processing system after the TBC. In this case, reset read pulses RRY and R
Preferably, the timing of at least one of the RCs can be arbitrarily adjusted.

c. Control of TBC operation The above-mentioned TBCIO and 11 can stop (turn off) their operation by the user's switch operation or according to the operating state of the VTR. FIG. 5 shows the configuration for controlling the TBC. , in FIG. 5, the part surrounded by a broken line is T
It represents an IC board 61 having a configuration related to the BC, and 62 is a system controller consisting of a microcomputer to control the operation of the VTR.

The system controller 62 is supplied with a detection signal SW corresponding to the state of the TBC on/off switch and a detection signal J/P that distinguishes between normal playback and variable speed playback in which the Jidda dial is operated.

For example, the high level of the detection signals SW and J/P indicates that the TBC operation is on, and the low level indicates that the TBC operation is off.The system controller 62 outputs control signals S1, S2, and S3 related to the TBC. Ru. A high level of the control signal S1 means that the VTR is in recording operation. The control signal S2 is a signal for controlling on/off of the TBC. The control signal S3 is transmitted through the frequency dividing circuit 36
This is the reset signal for This reset operation causes the phase of the output signal of the frequency divider circuit 36 to be synchronized with the control signal S3.

As mentioned above, the output signal of the crystal oscillator 14 is divided by the frequency dividing circuit 36 so that the frequencies on the writing side and the reading side of the TBC are matched on average. The output signal of the zero frequency divider circuit 36, which is used as a servo reference signal, is supplied to the reference signal generation circuit 65 via the reproduction side terminal p of the switch circuit 63 and the switch circuit 64.

The reference signal generation circuit 65 has a PLL configuration and generates a servo reference signal REF synchronized with the signal supplied via the switch circuit 64.

Servo reference signal REF is supplied to drum phase servo circuit 66. In the drum phase servo circuit 66, the detection signal PG indicating the rotational phase of the drum and the servo reference signal REF are compared in phase to form a phase error signal. Also,
A speed error signal is generated by a drum speed servo circuit 67, which is supplied with a detection signal FG of a frequency proportional to the rotational speed of the drum. The adder circuit 68 adds the phase error signal and the speed error signal, and the output signal of the adder circuit 68 is supplied to the D/A converter 70 via the amplifier 69.

An analog drive signal from the D/A converter 70 is supplied to the drum motor 38 via an integrating circuit 71. Further, a switching pulse Ps is formed from the detection signal PC, and the switching pulse Ps is supplied to the system controller 62.

Further, a swing pulse Ps is supplied from the system controller 62 to the IC board 61.

The switch circuit 63 is controlled by a control signal Sl from the system controller 62. During recording, a vertical synchronization signal separated from the recording video signal by the synchronization separation circuit 72 is supplied to the switch circuit 64 via the recording side terminal r of the switch circuit 63.

The switch circuit 64 is turned on when the output of the OR gate 73 is at a high level. The OR gate 73 is supplied with control Il signals S1 and S2 from the system controller 62. Therefore, during recording, the switch circuit 64 is turned on, and the reference signal generating circuit 65 generates a servo base signal REF synchronized with the vertical synchronizing signal in the recording video signal.

When the control signal S2 is at a high level during reproduction, the output signal of the frequency dividing circuit 36 is supplied to the reference signal generating circuit 65 via the switch circuits 63 and 64.

Therefore, the servo reference signal REF synchronized with the output signal of the frequency dividing circuit 36 is generated. In this case, the frequencies of the TBC write clock and read clock are matched on average.

The control signal S2 is supplied to the OR gate 73, and
The signal is supplied to a delay circuit 74. The control signal s4 delayed by the time L2 by the delay circuit 74 is supplied to the switch circuit 75 provided in the timing generation circuit 35. The switch circuit 75 switches the write clock WCK. As described above, one input terminal of the switch circuit 75 is connected to P.
A clock CKI synchronized with the reproduced signal from the LL 34 (see FIG. 2) is supplied, and a fixed frequency clock CK2 similar to the read clock is supplied to the other input terminal. As write clock WCK, clock CK
TBC operation is performed when I is selected. On the other hand, when the clock CK2 is selected as the write clock, only a fixed delay (3H for the luminance signal and 2H for the low frequency conversion color signal) occurs in the buffer memories 4o and 46 of TBCIO and 11, respectively. It is. In other words,
TBC operation is turned off.

The operation of the configuration shown in FIG. 5 will be described with reference to the timing chart shown in FIG. FIG. 5A shows a detection signal sw indicating the state of the operation switch. FIG. 5B shows a switching pulse Ps synchronized with the rotational phase of the drum.

After the user operates the switch and the detection signal sw rises to a high level, the switching pulse Ps causes the control signal s3 shown in FIG. 6C to be sent to the system controller 62.
is formed. The falling edge of this control signal S3 has a delay of a predetermined time t1 from the edge of the switching pulse Ps. The frequency dividing circuit 36 is reset at the fall of the control signal s3. After this reset, the phase of the output signal of the frequency dividing circuit 36 has the same phase as the falling edge of the control signal s3.

The control signal S2 rises from the fall of the control signal S3, and when the detection signal SW becomes low level, the control signal S2 falls. The delay circuit 74 obtains a control signal S4 delayed by a time t2 with respect to the control signal S2. When the control signal S2 becomes high level, the switch circuit 64 is turned on and the output signal of the frequency dividing circuit 36 is supplied to the reference signal generating circuit 65.

When the TBC is off, the servo reference signal REF from the reference signal generation circuit 65 and the rotational phase of the drum, that is, the phase of the switching pulse Ps, are defined to have a -constant relationship. The delay time (
1 is set. Therefore, TBC is turned on from off, and as a result, the reference signal generation circuit 65 and the frequency dividing circuit 36
Even when an output signal of

When the control ffl signal S4 becomes high level, the switch circuit 75 selects the clock CKI synchronized with the reproduced signal as the write clock WCK, and the TBC operation is turned on. The delay time L2 of the delay circuit 74 is set to a time necessary to prevent the TBC from operating when the drum servo is unstable.

Fig. 6 shows an example in which the TBC is turned on and off by operating a switch. Even if the switch is set to turn the TBC on, in jog mode, the detection signal J/P will cause the TBC to turn on and off in the same way as described above. , TBC is turned off. In jog mode, variable speed playback such as slow playback, still playback, cue playback, review playback, etc. is performed by operating the jog dial. During variable speed playback, the frequency of the horizontal synchronization signal of the playback signal deviates from the specified value, making TBC operation difficult.For this reason, TBC is turned off in jog mode.Even when returning from jog mode to normal playback operation, detection signal J/P changes. Therefore, the TBC off state is controlled to the TBC on state by the same operation as described above.

〔Effect of the invention〕

In this invention, the same time axis compensation as the playback video signal is performed on the dropout pulse, so when compensating for dropout on the output side of the TBC, a time lag occurs between the playback video signal and the dropout pulse. can be prevented from happening.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a TBC in this embodiment, and FIG. 3 is an example of a buffer memory used in the TBC. 4 is a timing chart of control signals for the buffer memory, and FIG. 5 is a block diagram of TBC.
FIG. 6 is a block diagram showing a configuration related to operation control, and FIG. 6 is a timing chart for explaining the operation of FIG. 5. Explanation of main symbols in the drawings 1: FM modulated luminance signal input terminal, 1O111: TBC. 13: Input terminal of low frequency conversion color signal, input terminal of Tobals, 31: Drop Array 36: Frequency division circuit, 37: Drum servo circuit, 38 Ni-drum motor, 40.46: Buffer memory, 62 Ni-system controller, 65: Standard Signal generation circuit, 75: Switch circuit.

Claims (1)

[Claims] Consisting of a memory and a controller that controls writing and reading of the memory, the reproduction signal is written into the memory with a clock synchronized with the reproduction signal reproduced by a magnetic head, and the reproduction signal is reproduced with a stable clock. a first TBC that reads a signal from the memory; and a memory that is supplied with a dropout pulse detected from the reproduced signal, and the memory is connected to the first TBC.
a second TBC controlled by the controller, and a second TBC provided on the output side of the first TBC;
A video signal reproducing device comprising a dropout compensation circuit controlled by the dropout pulse outputted from C.