JPS5917570B2 - Multiplexing circuit using PLL - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a clock signal for reproducing waveforms in a multiplexing circuit;
The present invention relates to a multiplexing circuit using L (Phase Locked Loop).

FIG. 1A is a block diagram showing the configuration of a PCM wireless transmission system, in which 1 is a PCM line monitoring device O (sending end), 2 is a PCM multiplex radio device (sending end), and 3 is a PCM multiplex radio device ( 4 is a PCM line monitoring device (receiving end) having a multiplexing circuit using a PLL.

To explain the operation of this system, at the sending end, the 5PCM line monitoring device (sending end) 1 divides the PCM signal CH from the carrier end into two streams, and each frame is used to judge the line quality of the wireless transmission path. A frame synchronization signal and a line monitoring signal are superimposed on this, and PCM is sent as CHI and CH2.
Connect to multiplex radio 0 equipment (transmitting end) 2, where 4-phase P
Performs SK modulation and transmits wirelessly.

At the receiving end, two series of PCM signals CHI and CH2 from a PCM multiplex radio device (receiving end) 3 are connected to a PCM line monitoring device (receiving end) 4, where frame synchronization signals and line monitoring signals are transmitted. is extracted, and the quality of the wireless line is determined.

Furthermore, a multiplexing circuit using a PLL removes the frame synchronization signal and line monitoring signal, and creates two series of signals CHI and CH.
2 into one series of signals CH and send it again to the carrier end. 'O Here, the multiplexing circuit using a PLL used in the PCM line monitoring device (receiving end) 4 requires a multiplier circuit for the output of the PLL. In other words, the sending end synchronizes the n-sequence signal, superimposes a synchronization signal, etc., converts it into an m-sequence, and sends it out, and the receiving end uses '5 PLL to synchronize and remove the synchronization signal. When converting a sequence signal into n sequences, the multiplexed waveform reproducing circuit requires a clock signal multiplied by m/n.

In such a multiplier circuit, since the output phase is uncertain with respect to the original signal, a phase adjustment circuit is generally required after the multiplier circuit.

FIG. 1B is a block diagram showing the configuration of a multiplexing circuit using a conventional PLL.

In the figure, the case where n-1 and m=2 is illustrated. Further, FIG. 2 is a time chart showing signals of various parts in FIG. 1B. In the case of FIG. 1B, on the sending end side (not shown), one series of signals CH is transmitted using the staff synchronization method.
Two series of signals CHl on which frame synchronization signals etc. are superimposed,
Convert to CH2 and send.

In FIG. 2, A and b indicate such two series of signals CHl and CH2, respectively.

Signals CHl and CH2 each consist of l-bit signals,
A frame synchronization signal is inserted at the (1+1)th bit. In Figure 2 a, 1 to 9, 10 to 18,...
...indicates the data signal of each frame, and F
1, F2, . . . indicate frame synchronization signals. Similarly, in Figure 2b, V~9', 1σ~1
8'', . . . indicate data signals of each frame, and F1'', F2', . . . indicate frame synchronization signals. On the receiving side, two synchronized series of input signals CH1 and CH2 are input to a memory device (MEM) 1 having two k-bit elastic memories.

The skip pulse control circuit (PC) 2 controls the input clock FiCL (FIG. 2c) in accordance with the frame synchronization pulse EP to eliminate the same time slot as the frame synchronization signal. The input clock signal from which the same time slot as the frame synchronization signal has been removed is frequency-divided by k in the k-divider circuit (1/k) 3, and is used as the write clock W for the memory device 1.
CL is generated, whereby the signals CHl and CH2 are written into the memory device 1 with the synchronization signal removed. On the other hand, k
The frequency dividing circuit (1/k) 4 is a voltage controlled crystal oscillator (CXO).
) 5 is divided by k to generate a read clock RCL. The read clock RCL is given to a multiplexing circuit (MUX) 6, whereby the contents of the memory device 1 are read out and sent to the multiplexing circuit (MUX) 6.
Two series of signals CH' and CHZ from which frame synchronization pulses and the like have been removed are obtained from the outputs of (FIG. 2D and e). A phase comparator (PD) 7 compares the phases of the output of the k frequency divider circuit 3 and the output of the k frequency divider circuit 4, and generates an output according to the phase difference. The output of the phase comparator 7 is applied as a control signal to the voltage controlled crystal oscillator 5 via a low frequency waveform generator (LPE) 8 to control its oscillation frequency. The read clock RCL is thereby controlled to have an average frequency equal to the write clock WCL. Voltage controlled crystal oscillator 5, k frequency divider circuit 4,
The phase comparator 7 and the low frequency wave generator 8 constitute a PLL.
Two series of signals CHV from which frame synchronization pulses etc. have been removed
, CH2/ are input to the parallel conversion circuit (P/S) 9, and V
The CXO output clock FOCL performs parallel-to-serial conversion into one series of signals CH'', and the signal CH' is further applied to a waveform reproducing circuit (REG) 10.

In FIG. 2, F and g indicate the positive phase signal of the VCXO output clock FOCL and the negative phase signal obtained by inverting this, respectively, and h indicates the VCXO output clock FOCL.
Signals CHl″, C correspond to the positive and negative phase signals of L
It shows one series of signals CH' generated by parallel-to-serial conversion of H7.

On the other hand, the VCXO output clock FOCL is a doubler circuit (X
2) Added to 11 and multiplied by 2.

In FIG. 2, i indicates a signal generated by being doubled in this manner. The doubled signal is sent to a delay circuit (DL
) 12 to produce an output clock 2f0CL (FIG. 2j).

The output clock 2f0CL is applied to the waveform reproducing circuit 10 to reproduce the waveform of the signal CH' and generate the output signal CH.
At this time, it is necessary that the phase of the output clock 2f0CL has an appropriate constant phase relationship with respect to the signal CHI whose waveform is to be reproduced. However, the VCXO output clock FO
CL passes through the doubler circuit 11, which is an analog circuit, so that the phase of the output clock 2f0CL becomes uncertain.

Therefore, a delay circuit 12 is provided to reproduce the signal C whose waveform is to be reproduced.
H! It is necessary to keep the phase relationship between the output clock 2f0CL and the output clock 2f0CL constant. In FIG. 1B, the portions indicated by double-lined arrows indicate portions where the phase relationship between the data and the clock signal is uniquely determined based on the operation of the PLL. The present invention aims to eliminate such drawbacks of the prior art, and its purpose is to be able to always maintain a constant phase relationship between the data to be reproduced in waveform and the clock signal, and therefore to eliminate phase adjustment. The object of the present invention is to provide a circuit system that does not require any circuits. To achieve this objective, in the multiplexing circuit using the PLL of the present invention, the synchronization signal is removed while synchronizing the m (m is a positive integer) series of signals on which the synchronization signal is superimposed using the PLL. In a multiplexing circuit that converts signals into n (n is a positive integer) series of signals,
The output of the voltage controlled crystal oscillator that constitutes the PLL is expressed as m/n (
m/n is a positive integer);
An m/n frequency dividing circuit that divides the output of the n multiplier circuit by m/n is provided, and the output of the m/n frequency dividing circuit is fed back to the phase comparator, and the voltage control crystal is controlled by the output of the phase comparator. A PLL is configured by controlling an oscillator, and the m/n
The present invention is characterized in that the waveforms of the n-series signals are reproduced by the output of the multiplier circuit. Examples will be described below.

FIG. 3 is a block diagram showing the configuration of an embodiment of a multiplexing circuit using a PLL according to the present invention.

In this figure, the same parts as in FIG. 1B are indicated by the same numbers and symbols, and 13 is a divide-by-2 circuit (
/2). Further, in FIG. 3, the operation when signals CH', CH7 from which frame synchronization pulses and the like have been removed are output is the same as that in FIG. 1B. The VCXO output clock FOCL generated from the voltage controlled crystal oscillator 5 is
It is added to the doubler circuit 11 and multiplied by 2 to obtain the output clock 2f0CL.

The output clock 2f0CL is applied to a divide-by-2 circuit 13 and divided by two to produce a clock signal FO'CL having the same frequency as the VCXO output clock FOCL. The k-divider circuit 4 divides the signal FO'CL by k to generate a read clock RCL. Read clock RCL and write clock WCL
The phase is compared with the phase comparator 7, and an output corresponding to the phase difference is generated. This output is applied as a control signal to the voltage controlled crystal oscillator 5 via a low frequency wave generator 8 to control its oscillation frequency, so that the write clock WCL and the read clock RCL have the same average frequency. controlled. The voltage controlled crystal oscillator 5.2 multiplier circuit 11, 2 frequency divider circuit 13, k frequency divider circuit 4, phase comparator 7, and low frequency wave generator 8 constitute a PLL. Further, the two series of signals CHl' and CH2l outputted from the multiplexing circuit 6 are converted into parallel to serial by the clock signal FO'CL whose frequency is divided by 2.
A series of signals CH'' are generated, and the signal CH' is further applied to the waveform reproducing circuit 9 and the waveform is reproduced by the output clock 2f0CL to generate the output signal CH. At this time, the waveform of the reproduced signal CH' and the output clock 2f0CL are The phase of is P
Uniquely determined by LL. Therefore, in the circuit of FIG. 3, a phase adjustment circuit as in the case of FIG. 1 is unnecessary. In FIG. 3, the individual portions indicated by double-lined arrows indicate portions where the phase relationship between the data and the clock signal is uniquely determined. Furthermore, the time relationships among the various signals shown in the time chart of FIG. 2 are substantially the same in the embodiment of FIG. 3. However, (f) FOCL (correct) is (
f) FO'CL (positive), (g) FOCL (negative) is FO'
CL (negative), and the waveform of the double output of (1) disappears. As explained above, according to the multiplexing circuit using the PLL of the present invention, even if there is a phase uncertain part such as a doubler circuit in the PLL loop, the two series that are input to the parallel-serial conversion circuit signals CHV and CH7, a clock signal FO'CLl whose frequency is divided by 2, a series of signals CH/ which is the output of the parallel-to-serial conversion circuit, and an output clock 2f0CL.
The phase relationship of is always constant based on the operation of the PLL.
Therefore, unlike the conventional multiplexing circuit using PLL, there is no need for a phase adjustment circuit after the doubler circuit. Furthermore, even if the output phase of the doubler circuit fluctuates due to power supply voltage fluctuations, temperature fluctuations, aging, etc., the mutual phase relationship between the data signal and the clock signal is always constant, making it possible to create an extremely stable multiplexing circuit. It can be realized.

[Brief explanation of drawings]

Figure 1A is a block diagram showing the configuration of a PCM wireless transmission system, Figure 1B is a block diagram showing the configuration of a multiplexing circuit using a conventional PLL, and Figure 2 is a time chart showing the signals of each part in Figure 1B. , FIG. 3 is a block diagram showing the configuration of an embodiment of a multiplexing circuit using a PLL according to the present invention. 1... PCM line monitoring device (sending end), 2...
... PCM multiplex radio equipment (transmission end), 3...
・PCM multiplex radio equipment (receiving end), 4...PL
PCM line monitoring device with multiplexing circuit using L (
(receiving end), 1...Memory device (MEM), 2...
...Toothless pulse control circuit (PC), 3, 4...
. . . k frequency dividing circuit k), 5. ．． ...Voltage controlled crystal oscillator (VCXO), multiplexing circuit (MUX), 7...
...phase comparator), 8...low frequency wave filter (LPF)
), 9...column conversion circuit (P/S), 10...
...Waveform reproduction 11...2 multiplier circuit (X2),
(DL), 13...2 frequency divider circuit (x1/2).

Claims (1)

[Claims] 1. A multiplexing circuit that removes the synchronization signal from an m (m is a positive integer) series signal on which a synchronization signal is superimposed while synchronizing using a PLL, and then converts it into an n (n is a positive integer) series signal. , an m/n multiplier circuit that multiplies the output of the voltage controlled crystal oscillator constituting the PLL by m/n (m/n is a positive integer), and an m/n multiplier circuit that divides the output of the m/n multiplier circuit by m/n. /n
A PLL is configured by providing a frequency dividing circuit, feeding back the output of the m/n frequency dividing circuit to a phase comparator, and controlling a voltage controlled crystal oscillator by the output of the phase comparator. A multiplexing circuit using a PLL, characterized in that the waveform of the n series of signals is regenerated by the output of an m/n multiplier circuit.