JPH0328614Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an adapter for a synchronous modem having a multiplexing function.

[Conventional technology]

A synchronous modem sends data to the line in synchronization with a timing signal, and data from the line is
A timing signal is regenerated from the line reception signal, and sampled and extracted using the timing signal. The timing signal for transmission data may be supplied from the terminal to the modem (ST1) or from the modem to the terminal (ST2), but the timing signal for reception data (RT) is reproduced from the reception signal. In a synchronous modem that performs multiplexing, as shown in Figure 4, terminal device 1 and terminal device 2 are connected to the modem, data from these terminal devices is sent to the line, and data from the line is sent to these terminals. feed to the device. Terminal 1
The communication speed of terminal 2 is 2400bps, and the communication speed of terminal 2 is
Assuming 7200 bps, the modem sends the data sent by these terminals to the line at the sum of 9600 bps, and also sends the data sent from the line at 9600 bps to terminal 1 at 2400 bps and to terminal 2 at 2400 bps.
Send at 7200bps.

If terminal 1 is an ST1 terminal, two masters cannot exist at the same time, so terminal 2 is
The modem becomes an ST2 terminal, and the modem is supplied with a 2400bps timing signal from terminal 1, creates a 7200bps timing signal from this, and supplies it to terminal 2.
It also creates a 9600bps timing signal and uses this to send data from terminals 1 and 2 to the line.

[Problem that the invention attempts to solve]

In this way, when multiplexing data is transferred using terminal 1, which is a low-speed terminal, as the reference (master) and terminal 2, which is a high-speed terminal, as a slave, the timing signal for the high-speed terminal and line is transferred from the timing signal ST1 on the low-speed side. If you have a built-in modem, you can use the process described above to transfer data without any problems. However, some modems generate a timing signal for a low-speed terminal from a timing signal for a high-speed terminal, but do not do the reverse, and such modems cannot perform multiplex transmission with the low-speed terminal as the master. For example, making a low-speed terminal the master means that a low-speed network is set up, a high-speed network is set up separately from this (this includes both multiplexing and non-multiplexing), and the low-speed network is set up separately. This is necessary when connecting to high-speed networks and wanting the master of these networks to be the master of an existing low-speed network.

The present invention attempts to make it possible to easily deal with such cases without replacing the modem by providing an adapter to perform the conversion.

[Means for solving problems]

The synchronous modem adapter of the present invention has a low-speed master terminal, a high-speed slave terminal, and terminals to which the high-speed and low-speed terminals are connected, and receives high-speed timing signals from the high-speed terminal. connected to each terminal of an operating synchronous modem, and equipped with a frequency multiplier circuit, converting the low-speed timing signal output from the low-speed terminal device into the high-speed timing signal and outputting it to the high-speed terminal device and the high-speed terminal terminal of the modem. It is characterized by being made to do.

[Function and Examples]

Referring to FIG. 1, in the present invention, an adapter 10 is provided between the terminal and the modem. The adapter 10 is a frequency multiplier circuit, in this example a PLL (Phase Locked Loop).
12, and when it receives a low-speed timing signal ST1 of 2400bps in this example from terminal 1, it uses that as a base.
The PLL 12 generates a high-speed timing signal of 7200 bps in this example, and supplies it to the terminal 2 as ST2 and to the modem 20 as ST1 (the timing signal is different from the timing signal from terminal 1, so it is appended with ').
In the modem 20, the PLL 22 generates a low-speed timing signal ST2' based on the high-speed timing signal ST1' input to the terminal (channel) A.
(In First Out) The register 24 is read.
The data transmitted from terminal 1 is synchronized with the timing signal ST1 generated by itself, and this data
Written to FIFO register. FIFO register 24
Since the timing signal ST1 for writing and the timing signal ST2' for reading have the same frequency, there is no problem in taking in and taking out data from the register. FIFO is already installed in the modem,
Using this FIFO can eliminate phase shifts.
The data transmitted from the terminal 2 is synchronized with the timing signal ST2 sent from the adapter 10, and the modem 20 takes in this data using the same timing signal ST1' from the adapter 10, and then combines it with the data from the FIFO register 24 and the modem. In this example, it is multiplexed using a 9600bps timing signal and sent to the line.

FIG. 2 is a slightly more detailed diagram of the adapter 10.
16 is a high frequency (several hundred KHz) oscillator, and PLL
12 divides this in synchronization with the ST1 clock,
In this example, timing signals of 9600, 7200, and 4800 bps are generated. 14 is a switch that selects one of these timing signals and sends it to terminal 2.
2 and is also supplied to the modem 20 as ST1'. When the terminal has 4800 bps or 9600 bps, these are selected by the switch 14 and supplied to each. The terminal and modem are connected by one signal line in Figure 1 and several signal lines in Figure 2, but in reality they are connected by a sending data (SD) line, a receiving data (RD) line, and a sending request line ( RS), clear to send (CS) line, ...transmission signal element timing signal (ST ₁ , ST ₂ ) line,
The receiving signal element is connected by more than 10 signal lines, including timing signal (RT) lines.

The adapter 10 may be incorporated into the modem, but
It is convenient to put it in an independent case, provide connectors for terminals 1 and 2 and modem A and B terminals (channels), and connect them with cables as shown in the figure (there is no need to modify the terminals and modem). In this case, some signal lines simply pass through the adapter. The number of multiplexed terminals is not limited to two, and there are various combinations of communication speeds, so it goes without saying that the system should be adapted to these.

Since the power consumption of the adapter 10 is small, it can be sufficiently supplied by taking in electrical energy from various signal lines without providing a power line to supply power.
An example is shown in FIG. In the adapter 10, a group of diodes 32 with the polarity shown is connected to the signal line connecting the terminal 2 and the modem A side, and a group of diodes 34 with the polarity shown is connected to the signal line connecting the terminal 1 and the modem B side. Capacitor C ₁ between the diode group
When connected, the highest voltage is supplied from the diode group 32 and the lowest voltage is supplied from the diode group 34, so that the capacitor _C1 is charged by the difference between these voltages with the polarity shown. Since this capacitor voltage fluctuates slightly, it is made constant by a regulator 42, and +5V power is supplied through conductors 36 and 38. If two groups of diodes (but with opposite polarities) and a capacitor _C2 are similarly connected between these signal lines, the capacitors will be charged with the polarity shown,
This is made constant voltage by the regulator 44, and the conductor 3
-5V power can be supplied through 8,40. The signal line voltage is +5V to +15V and -5 to 15V.
Therefore, it is easy to create +5V and -5V from these.

[Effect of idea]

As explained above, the present invention is extremely effective because it can easily configure a high-speed network using a TS1 terminal that outputs a low-speed timing signal as a master by using a modem that uses a high-speed timing signal as a master.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is an explanatory diagram showing details of the main parts of Fig. 1, Fig. 3 is a circuit diagram of the power supply device, and Fig. 4 explains the conventional system. It is a block diagram. In the drawing, 10 is an adapter, 20 is a modem, ST1,
ST2' is a low-speed timing signal, ST2 and ST1' are high-speed timing signals, and 12 is a frequency multiplier circuit.

Claims (1)

[Claims for Utility Model Registration] An adapter interposed between a synchronous modem and a plurality of terminal devices each operating at different data transmission speeds, the output of the terminal device operating at a lower speed among the terminal devices. a frequency multiplier circuit that generates a timing signal for a terminal device operating at high speed in synchronization with a timing signal outputted by the low-speed terminal device; An adapter for a synchronous modem, characterized in that it is configured to output to.