JPS61168740U - - Google Patents
Info
- Publication number
- JPS61168740U JPS61168740U JP5194285U JP5194285U JPS61168740U JP S61168740 U JPS61168740 U JP S61168740U JP 5194285 U JP5194285 U JP 5194285U JP 5194285 U JP5194285 U JP 5194285U JP S61168740 U JPS61168740 U JP S61168740U
- Authority
- JP
- Japan
- Prior art keywords
- terminal device
- timing signal
- output
- speed
- adapter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001360 synchronised effect Effects 0.000 claims 2
- 230000005540 biological transmission Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Description
第１図は本考案の実施例を示すブロツク図、第
２図は第１図の要部の詳細を示す説明図、第３図
は電源装置の回路図、第４図は従来方式を説明す
るブロツク図である。
図面で１０はアダプタ、２０はモデム、ＳＴ１
，ＳＴ２′は低速タイミング信号、ＳＴ２，ＳＴ
１′は高速タイミング信号、１２は周波数逓倍回
路である。
Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is an explanatory diagram showing details of the main parts of Fig. 1, Fig. 3 is a circuit diagram of the power supply device, and Fig. 4 explains the conventional system. It is a block diagram. In the drawing, 10 is an adapter, 20 is a modem, and ST1
, ST2' are low-speed timing signals, ST2, ST
1' is a high-speed timing signal, and 12 is a frequency multiplier circuit.
Claims (1)
動作する複数の端末装置との間に介設されるアダ
プタであつて、 端末装置のうち低速で動作する端末装置の出力
するタイミング信号に同期して高速で動作する端
末装置のタイミング信号を発生する周波数逓倍回
路を備え、前記低速の端末装置が出力する低速タ
イミング信号に同期した高速タイミング信号を前
記高速の端末装置及びモデムへ出力するようにさ
れてなることを特徴とする同期式モデム用のアダ
プタ。[Claims for Utility Model Registration] An adapter interposed between a synchronous modem and a plurality of terminal devices each operating at different data transmission speeds, the output of the terminal device operating at a lower speed among the terminal devices. a frequency multiplier circuit that generates a timing signal for a terminal device operating at high speed in synchronization with a timing signal outputted by the low-speed terminal device; An adapter for a synchronous modem, characterized in that it is configured to output to.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985051942U JPH0328614Y2 (en) | 1985-04-08 | 1985-04-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985051942U JPH0328614Y2 (en) | 1985-04-08 | 1985-04-08 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61168740U true JPS61168740U (en) | 1986-10-20 |
| JPH0328614Y2 JPH0328614Y2 (en) | 1991-06-19 |
Family
ID=30571443
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985051942U Expired JPH0328614Y2 (en) | 1985-04-08 | 1985-04-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0328614Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56110363A (en) * | 1980-02-06 | 1981-09-01 | Fujitsu Ltd | Multiplexing circuit using pll |
-
1985
- 1985-04-08 JP JP1985051942U patent/JPH0328614Y2/ja not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56110363A (en) * | 1980-02-06 | 1981-09-01 | Fujitsu Ltd | Multiplexing circuit using pll |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0328614Y2 (en) | 1991-06-19 |
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