JPS58119253U - 2-wire half-duplex communication modem - Google Patents
2-wire half-duplex communication modemInfo
- Publication number
- JPS58119253U JPS58119253U JP12645581U JP12645581U JPS58119253U JP S58119253 U JPS58119253 U JP S58119253U JP 12645581 U JP12645581 U JP 12645581U JP 12645581 U JP12645581 U JP 12645581U JP S58119253 U JPS58119253 U JP S58119253U
- Authority
- JP
- Japan
- Prior art keywords
- data
- duplex communication
- communication modem
- wire half
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Bidirectional Digital Transmission (AREA)
- Communication Control (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のモデムを説明するためのブロック図。第
２図は従来のモデムの動作を説明するための多イミング
チヤード。第３図は本考案のモデムを説明するためのブ
ロック図。第４図は本考案モデルの要部ブロック図。第
５図は本考案モデムの動作を説明するためのタイミング
チャートであ、 る。
２０・・・・・・（本考案の）モデム、２１・・・・・
・データ復調回路、２２・・・・・・遅延回路、２３・
・・・・・シフトレジスタ、２４・・・・・・クロック
パルス発生回路。
（１０）
（″−リアリー
ｑじ司ｆ”ｙＹｔ）
（−ラＹ２）
（１４）
（キャリアｘ２）。
（５）−−
１ｔ１−
Ａｔ２−ｔ、し ゛FIG. 1 is a block diagram for explaining a conventional modem. FIG. 2 is a multi-imaging yard for explaining the operation of a conventional modem. FIG. 3 is a block diagram for explaining the modem of the present invention. Figure 4 is a block diagram of the main parts of the proposed model. FIG. 5 is a timing chart for explaining the operation of the modem of the present invention. 20...Modem (of the present invention), 21...
・Data demodulation circuit, 22...Delay circuit, 23.
...Shift register, 24...Clock pulse generation circuit. (10) (″-Real qjijif”yYt) (-RaY2) (14) (Carrier x2). (5) -- 1t1- At2-t, ゛
Claims (1)
回路に直列に、前記データを所定時間遅延させる遅延回
路を接続し、データを遅延させてデータ送受装置へ送出
することを特徴とする２線式半二重通信用モデム。A delay circuit that delays the data for a predetermined time is connected in series with a data demodulation circuit that takes in and demodulates data from a two-wire line, and the data is delayed and sent to the data transmitting/receiving device. Modem for wire half-duplex communication.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12645581U JPS58119253U (en) | 1981-08-28 | 1981-08-28 | 2-wire half-duplex communication modem |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12645581U JPS58119253U (en) | 1981-08-28 | 1981-08-28 | 2-wire half-duplex communication modem |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58119253U true JPS58119253U (en) | 1983-08-13 |
Family
ID=30101390
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12645581U Pending JPS58119253U (en) | 1981-08-28 | 1981-08-28 | 2-wire half-duplex communication modem |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58119253U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02285750A (en) * | 1989-04-26 | 1990-11-26 | Toshiba Electric Appliance Co Ltd | Communication controller |
-
1981
- 1981-08-28 JP JP12645581U patent/JPS58119253U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02285750A (en) * | 1989-04-26 | 1990-11-26 | Toshiba Electric Appliance Co Ltd | Communication controller |
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