JPS63142937U - - Google Patents

Info

Publication number
JPS63142937U
JPS63142937U JP3490687U JP3490687U JPS63142937U JP S63142937 U JPS63142937 U JP S63142937U JP 3490687 U JP3490687 U JP 3490687U JP 3490687 U JP3490687 U JP 3490687U JP S63142937 U JPS63142937 U JP S63142937U
Authority
JP
Japan
Prior art keywords
clock signal
receiving device
generation means
terminal devices
data transmitting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3490687U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3490687U priority Critical patent/JPS63142937U/ja
Publication of JPS63142937U publication Critical patent/JPS63142937U/ja
Pending legal-status Critical Current

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  • Synchronisation In Digital Transmission Systems (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す説明図。第2
図a,bは本考案の一実施例に使用されるコネク
ターを示す説明図。第3図は接続ケーブルの接続
状態を示す説明図。第4図はデータ信号を示す説
明図。第5図a,b,cは本考案の一実施例にお
けるタイミングチヤート。 1……MODEM、2……パソコン、3……ケ
ーブル、4a,4b……コネクター。
FIG. 1 is an explanatory diagram showing an embodiment of the present invention. Second
Figures a and b are explanatory diagrams showing a connector used in an embodiment of the present invention. FIG. 3 is an explanatory diagram showing the connection state of the connection cable. FIG. 4 is an explanatory diagram showing data signals. FIGS. 5a, b, and c are timing charts in one embodiment of the present invention. 1...MODEM, 2...PC, 3...cable, 4a, 4b...connector.

Claims (1)

【実用新案登録請求の範囲】 クロツク信号を発生する単一のクロツク信号発
生手段と、データを送受信する複数の端末機器よ
り構成され、 前記複数の端末機器が前記単一のクロツク信号
発生手段より出力される前記クロツク信号を共用
できるようにケーブルによつて接続されたことを
特徴とする同期式データ送受信装置。
[Claims for Utility Model Registration] Consisting of a single clock signal generation means that generates a clock signal and a plurality of terminal devices that transmit and receive data, the plurality of terminal devices output from the single clock signal generation means. 1. A synchronous data transmitting/receiving device, characterized in that the data transmitting and receiving device is connected by a cable so that the clock signal transmitted by the two devices can be shared.
JP3490687U 1987-03-10 1987-03-10 Pending JPS63142937U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3490687U JPS63142937U (en) 1987-03-10 1987-03-10

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3490687U JPS63142937U (en) 1987-03-10 1987-03-10

Publications (1)

Publication Number Publication Date
JPS63142937U true JPS63142937U (en) 1988-09-20

Family

ID=30843898

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3490687U Pending JPS63142937U (en) 1987-03-10 1987-03-10

Country Status (1)

Country Link
JP (1) JPS63142937U (en)

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