JPS6356833U - - Google Patents
Info
- Publication number
- JPS6356833U JPS6356833U JP14971086U JP14971086U JPS6356833U JP S6356833 U JPS6356833 U JP S6356833U JP 14971086 U JP14971086 U JP 14971086U JP 14971086 U JP14971086 U JP 14971086U JP S6356833 U JPS6356833 U JP S6356833U
- Authority
- JP
- Japan
- Prior art keywords
- sample clock
- converter
- external sample
- signal indicating
- external
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007257 malfunction Effects 0.000 claims 3
- 230000002265 prevention Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
- 238000007493 shaping process Methods 0.000 description 1
Description
第１図は本考案の一実施例を示す構成図、第２
図は本考案の一実施例における動作波形図である
。
１……外部サンプルクロツク整形回路、２……
論理積（ＡＮＤ）回路、３……ＡＤコンバータ、
４……クロツクジエネレータ、５……単安定マル
チバイブレータ、６……表示装置、ＥＸＴＣＬＫ
，ＥＸＣＬ，ＥＣ……外部サンプルクロツク、Ａ
ＤＲＤＹ……サンプルクロツク受入れ可能状態を
示す信号、ＧＣ……同期信号、ＯＳ……単安定マ
ルチバイブレータ出力信号。
Figure 1 is a configuration diagram showing one embodiment of the present invention;
The figure is an operational waveform diagram in one embodiment of the present invention. 1...External sample clock shaping circuit, 2...
Logical product (AND) circuit, 3...AD converter,
4... Clock generator, 5... Monostable multivibrator, 6... Display device, EXTCLK
, EXCL, EC...external sample clock, A
DRDY: Signal indicating sample clock acceptance state, GC: Synchronization signal, OS: Monostable multivibrator output signal.
Claims (1)
の受け入れ可能状態を示す信号を出力し、該信号
と外部サンプルクロツクパルスとの論理積をとつ
て前記ＡＤコンバータへ外部サンプルクロツクと
して与え、前記ＡＤコンバータが外部サンプルク
ロツクの受入れ不可能な状態のときに、入力され
る外部サンプルクロツクパルスを打消すと共に、
該サンプルクロツクが速すぎることを表わす信号
を得るように構成したことを特徴とするＡＤコン
バータ誤動作防止装置。 (2) 前記サンプルクロツクが速すぎることを表
わす信号は、前記サンプルクロツクの速度が前記
ＡＤコンバータに対して、誤動作を起さない程度
に遅くなつたとき、これに呼応して切換えられる
ことを特徴とする実用新案登録請求の範囲第１項
記載のＡＤコンバータ誤動作防止装置。[Claims for Utility Model Registration] (1) The AD converter outputs a signal indicating a state in which the external sample clock can be accepted, and the signal is ANDed with the external sample clock pulse to send the external sample to the AD converter. and cancels the input external sample clock pulse when the AD converter is in a state where it cannot accept the external sample clock;
An AD converter malfunction prevention device characterized in that it is configured to obtain a signal indicating that the sample clock is too fast. (2) The signal indicating that the sample clock is too fast is switched in response to the time when the speed of the sample clock becomes slow enough to prevent malfunction with respect to the AD converter. An AD converter malfunction prevention device according to claim 1 of the utility model registration claim, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14971086U JPS6356833U (en) | 1986-09-30 | 1986-09-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14971086U JPS6356833U (en) | 1986-09-30 | 1986-09-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6356833U true JPS6356833U (en) | 1988-04-15 |
Family
ID=31065178
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14971086U Pending JPS6356833U (en) | 1986-09-30 | 1986-09-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6356833U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51129165A (en) * | 1975-05-02 | 1976-11-10 | Teraoka Seiko Co Ltd | Detect system of abnormal reading speed by a-d converter |
-
1986
- 1986-09-30 JP JP14971086U patent/JPS6356833U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51129165A (en) * | 1975-05-02 | 1976-11-10 | Teraoka Seiko Co Ltd | Detect system of abnormal reading speed by a-d converter |
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