JPS6251866U - - Google Patents

Info

Publication number
JPS6251866U
JPS6251866U JP14397685U JP14397685U JPS6251866U JP S6251866 U JPS6251866 U JP S6251866U JP 14397685 U JP14397685 U JP 14397685U JP 14397685 U JP14397685 U JP 14397685U JP S6251866 U JPS6251866 U JP S6251866U
Authority
JP
Japan
Prior art keywords
multivibrator
logic gate
synchronization detection
horizontal synchronization
horizontal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14397685U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14397685U priority Critical patent/JPS6251866U/ja
Publication of JPS6251866U publication Critical patent/JPS6251866U/ja
Pending legal-status Critical Current

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  • Synchronizing For Television (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の1実施例の回路構成図、第2
図及び第3図はともに同実施例の動作説明のため
の信号波形図、第4図乃至第6図はそれぞれ本考
案の他の実施例の回路構成図、第7図は従来例の
ブロツク図である。 1…単安定マルチバイブレータ、2,2′,2
″,2…論理ゲート。
Fig. 1 is a circuit diagram of one embodiment of the present invention;
3 and 3 are both signal waveform diagrams for explaining the operation of the same embodiment, FIGS. 4 to 6 are circuit configuration diagrams of other embodiments of the present invention, and FIG. 7 is a block diagram of the conventional example. It is. 1... Monostable multivibrator, 2, 2', 2
″, 2…Logic gate.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] H/2〈τ〈H(但しHは1水平周期)なる関
係式を満足する時定数τを有する単安定マルチバ
イブレータと、該マルチバイブレータの出力と同
期分離後の複合同期信号との論理演算をする論理
ゲートとを備え、該論理ゲートより前記マルチバ
イブレータのトリガー入力を得るとともに水平同
期検出信号を得ることを特徴とする水平同期検出
回路。
A monostable multivibrator with a time constant τ that satisfies the relational expression H/2〈τ〈H (where H is one horizontal period), and a logical operation between the output of the multivibrator and the composite synchronous signal after synchronous separation. 1. A horizontal synchronization detection circuit, comprising: a logic gate for obtaining a trigger input for the multivibrator and a horizontal synchronization detection signal from the logic gate.
JP14397685U 1985-09-19 1985-09-19 Pending JPS6251866U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14397685U JPS6251866U (en) 1985-09-19 1985-09-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14397685U JPS6251866U (en) 1985-09-19 1985-09-19

Publications (1)

Publication Number Publication Date
JPS6251866U true JPS6251866U (en) 1987-03-31

Family

ID=31054159

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14397685U Pending JPS6251866U (en) 1985-09-19 1985-09-19

Country Status (1)

Country Link
JP (1) JPS6251866U (en)

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