JPS6344535U - - Google Patents
Info
- Publication number
- JPS6344535U JPS6344535U JP13752486U JP13752486U JPS6344535U JP S6344535 U JPS6344535 U JP S6344535U JP 13752486 U JP13752486 U JP 13752486U JP 13752486 U JP13752486 U JP 13752486U JP S6344535 U JPS6344535 U JP S6344535U
- Authority
- JP
- Japan
- Prior art keywords
- counter
- output
- flop
- flip
- detection means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Programmable Controllers (AREA)
Description
第１図は本考案に係るプログラマブルカウンタ
の一実施例を示すブロツク図、第２図、第３図は
動作を説明するためのタイムチヤート、第４図は
従来例のブロツク図、第５図は第２カウンタの構
成を示すブロツク図、第６図は従来例の動作を説
明するためのタイムチヤートである。
１，１０……第１のカウンタ、２……第２のカ
ウンタ、３，１２，１３……検出手段、４……設
定器、５……カウンタ、１１……フリツプフロツ
プ。
FIG. 1 is a block diagram showing an embodiment of the programmable counter according to the present invention, FIGS. 2 and 3 are time charts for explaining the operation, FIG. 4 is a block diagram of a conventional example, and FIG. FIG. 6 is a block diagram showing the configuration of the second counter, and a time chart for explaining the operation of the conventional example. 1, 10...first counter, 2...second counter, 3, 12, 13...detection means, 4...setting device, 5...counter, 11...flip-flop.
Claims (1)
１のカウンタの出力が入力されるフリツプフロツ
プと、前記第１のカウンタおよびフリツプフロツ
プの出力が所定の値になつたことを検出する検出
手段と、この検出手段の出力が入力される第２の
カウンタとを有し、前記第２のカウンタの出力が
所定の値になりかつ前記検出手段の出力が出力さ
れたときに前記フリツプフロツプをセツトすると
ともに前記第１のカウンタおよび第２のカウンタ
に所定の値をセツトすることを特徴とするプログ
ラマブルカウンタ。 a first counter to which a clock is input; a flip-flop to which the output of the first counter is input; detection means for detecting that the outputs of the first counter and the flip-flop have reached predetermined values; and a second counter to which the output of the detection means is input, and when the output of the second counter reaches a predetermined value and the output of the detection means is output, the flip-flop is set and the flip-flop is set. A programmable counter characterized in that a predetermined value is set in a counter and a second counter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13752486U JPS6344535U (en) | 1986-09-08 | 1986-09-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13752486U JPS6344535U (en) | 1986-09-08 | 1986-09-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6344535U true JPS6344535U (en) | 1988-03-25 |
Family
ID=31041660
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13752486U Pending JPS6344535U (en) | 1986-09-08 | 1986-09-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6344535U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5011361A (en) * | 1973-05-30 | 1975-02-05 |
-
1986
- 1986-09-08 JP JP13752486U patent/JPS6344535U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5011361A (en) * | 1973-05-30 | 1975-02-05 |