JPS62203467U - - Google Patents
Info
- Publication number
- JPS62203467U JPS62203467U JP9112686U JP9112686U JPS62203467U JP S62203467 U JPS62203467 U JP S62203467U JP 9112686 U JP9112686 U JP 9112686U JP 9112686 U JP9112686 U JP 9112686U JP S62203467 U JPS62203467 U JP S62203467U
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- terminal
- input terminal
- pulse width
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
Description
第1図は本考案の一実施例のブロツク図、第2
図は第1図に示す実施例の動作を説明するための
タイム図、第3図は従来のパルス幅検出回路の一
例のブロツク図である。
1……正論理入力端、2……負論理入力端、3
……パルス幅設定回路、4……パルス幅設定端、
5……モノステーブル・マルチバイブレータ回路
、6……判定回路、7……判定出力端、8……反
転出力端、9……入力パルス入力端、10……基
準パルス入力端、15……基準パルス幅、16…
…被検出パルス幅、31……基準クロツク発生回
路、32……カウンタ回路、33……判定回路、
34……判定基準値、IN……入力パルス、OU
T,OUT′……判定信号、ST……基準パルス
。
Fig. 1 is a block diagram of an embodiment of the present invention;
1 is a time diagram for explaining the operation of the embodiment shown in FIG. 1, and FIG. 3 is a block diagram of an example of a conventional pulse width detection circuit. 1...Positive logic input terminal, 2...Negative logic input terminal, 3
...Pulse width setting circuit, 4...Pulse width setting end,
5... Monostable multivibrator circuit, 6... Judgment circuit, 7... Judgment output terminal, 8... Inverted output terminal, 9... Input pulse input terminal, 10... Reference pulse input terminal, 15... Reference Pulse width, 16...
...Detected pulse width, 31...Reference clock generation circuit, 32...Counter circuit, 33...Judgment circuit,
34... Judgment reference value, IN... Input pulse, OU
T, OUT'...Judgment signal, ST...Reference pulse.
Claims (1)
と出力端と反転出力端とを有し前記正論理入力端
又は負論理入力端のいずれかに印加される入力パ
ルスの前縁で発生し前記パルス幅設定端に与えら
れる基準の幅を有する基準パルスを出力するモノ
ステーブル・マルチバイブレータ回路と、入力パ
ルス入力端と基準パルス入力端と判定出力端とを
有し入力される前記基準パルスと入力パルスとの
パルス幅を比較して判定信号を出力する判定回路
とを含むことを特徴とするパルス幅検出回路。 It has a positive logic input terminal, a negative logic input terminal, a pulse width setting terminal, an output terminal, and an inverted output terminal, and is generated at the leading edge of an input pulse applied to either the positive logic input terminal or the negative logic input terminal. a monostable multivibrator circuit that outputs a reference pulse having a reference width given to the pulse width setting terminal; the monostable multivibrator circuit has an input pulse input terminal, a reference pulse input terminal, and a determination output terminal; A pulse width detection circuit comprising: a determination circuit that compares the pulse width with an input pulse and outputs a determination signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9112686U JPS62203467U (en) | 1986-06-13 | 1986-06-13 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9112686U JPS62203467U (en) | 1986-06-13 | 1986-06-13 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62203467U true JPS62203467U (en) | 1987-12-25 |
Family
ID=30951625
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9112686U Pending JPS62203467U (en) | 1986-06-13 | 1986-06-13 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62203467U (en) |
-
1986
- 1986-06-13 JP JP9112686U patent/JPS62203467U/ja active Pending