JPS6297964U - - Google Patents

Info

Publication number
JPS6297964U
JPS6297964U JP18942685U JP18942685U JPS6297964U JP S6297964 U JPS6297964 U JP S6297964U JP 18942685 U JP18942685 U JP 18942685U JP 18942685 U JP18942685 U JP 18942685U JP S6297964 U JPS6297964 U JP S6297964U
Authority
JP
Japan
Prior art keywords
reference clock
pulse
measured
asynchronous
pulse width
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18942685U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18942685U priority Critical patent/JPS6297964U/ja
Publication of JPS6297964U publication Critical patent/JPS6297964U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Manipulation Of Pulses (AREA)
  • Measurement Of Unknown Time Intervals (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一具体的実施例を示す非同期
式パルス幅測定回路のブロツク線図、第2図はタ
イムチヤート、第3図は従来の非同期式パルス幅
測定回路の構成を示すブロツク線図、第4図はタ
イムチヤートである。 1……ANDゲート、2……カウンタ回路、3
……マイクロコンピユータ(CPU)、4……判
別回路。
Fig. 1 is a block diagram of an asynchronous pulse width measuring circuit showing a specific embodiment of the present invention, Fig. 2 is a time chart, and Fig. 3 is a block diagram showing the configuration of a conventional asynchronous pulse width measuring circuit. Figure 4 is a time chart. 1...AND gate, 2...Counter circuit, 3
...Microcomputer (CPU), 4...Discrimination circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 基準クロツクに基づいてこの基準クロツクの周
期とは非同期の周期を有する被測定パルスのパル
ス幅を測定する非同期式パルス幅測定回路におい
て、前記基準クロツクと前記被測定パルスから前
記被測定パルスの立上がり及び立下がり時の基準
クロツクの状態を判別する判別回路を具備したこ
とを特徴とする非同期式パルス幅測定回路。
In an asynchronous pulse width measurement circuit that measures the pulse width of a pulse to be measured having a period asynchronous to the period of the reference clock based on a reference clock, the rise and rise of the pulse to be measured are determined from the reference clock and the pulse to be measured. An asynchronous pulse width measuring circuit characterized by comprising a discrimination circuit for discriminating the state of a reference clock at the falling edge.
JP18942685U 1985-12-09 1985-12-09 Pending JPS6297964U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18942685U JPS6297964U (en) 1985-12-09 1985-12-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18942685U JPS6297964U (en) 1985-12-09 1985-12-09

Publications (1)

Publication Number Publication Date
JPS6297964U true JPS6297964U (en) 1987-06-22

Family

ID=31141717

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18942685U Pending JPS6297964U (en) 1985-12-09 1985-12-09

Country Status (1)

Country Link
JP (1) JPS6297964U (en)

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