JPH0227237U - - Google Patents
Info
- Publication number
- JPH0227237U JPH0227237U JP10440188U JP10440188U JPH0227237U JP H0227237 U JPH0227237 U JP H0227237U JP 10440188 U JP10440188 U JP 10440188U JP 10440188 U JP10440188 U JP 10440188U JP H0227237 U JPH0227237 U JP H0227237U
- Authority
- JP
- Japan
- Prior art keywords
- interrupt
- signal
- flop
- counter
- interrupt request
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003708 edge detection Methods 0.000 claims description 3
- 230000014759 maintenance of location Effects 0.000 claims 1
- 230000000630 rising effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Bus Control (AREA)
Description
第１図は本考案の第１の実施例のブロツク図、
第２図は本考案の第２の実施例のブロツク図であ
る。
１…割込み信号、２…エツジ検出回路、３…割
込み要求フリツプフロツプ、４…基準クロツク信
号、５…ＡＮＤ回路、６…カウンタ、７…プリセ
ツトデータ設定回路、８…比較回路、９…割込み
要求信号、１０…リセツト信号、１１…割込み要
求選択信号、１２…選択回路、１３…反転回路、
１４，１５…ＡＮＤ回路、１６…ＯＲ回路、１７
…選択割込み要求信号。
FIG. 1 is a block diagram of the first embodiment of the present invention;
FIG. 2 is a block diagram of a second embodiment of the present invention. 1... Interrupt signal, 2... Edge detection circuit, 3... Interrupt request flip-flop, 4... Reference clock signal, 5... AND circuit, 6... Counter, 7... Preset data setting circuit, 8... Comparison circuit, 9... Interrupt request signal , 10... Reset signal, 11... Interrupt request selection signal, 12... Selection circuit, 13... Inversion circuit,
14, 15...AND circuit, 16...OR circuit, 17
...Selection interrupt request signal.
Claims (1)
ジ検出回路と、該エツジ検出回路の出力によりセ
ツト及びリセツトされる割込み要求フリツプフロ
ツプと、該割込み要求フリツプフロツプがセツト
されている間基準クロツク信号をベースとして前
記割込み信号のアクテイブレベルの保持時間を計
数するカウンタと、予め設定されたプリセツトデ
ータと前記カウンタの計数値とを比較して割込み
要求信号を出力する比較回路とを含むことを特徴
とする割込み制御回路。 an edge detection circuit that detects the rising and falling edges of an interrupt signal; an interrupt request flip-flop that is set and reset by the output of the edge detection circuit; and while the interrupt request flip-flop is set, the interrupt is detected based on the reference clock signal. An interrupt control circuit comprising: a counter that counts a signal's active level retention time; and a comparison circuit that compares preset data with a count value of the counter and outputs an interrupt request signal. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10440188U JPH0227237U (en) | 1988-08-05 | 1988-08-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10440188U JPH0227237U (en) | 1988-08-05 | 1988-08-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0227237U true JPH0227237U (en) | 1990-02-22 |
Family
ID=31336085
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10440188U Pending JPH0227237U (en) | 1988-08-05 | 1988-08-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0227237U (en) |
-
1988
- 1988-08-05 JP JP10440188U patent/JPH0227237U/ja active Pending