JPH0330131U - - Google Patents
Info
- Publication number
- JPH0330131U JPH0330131U JP8971389U JP8971389U JPH0330131U JP H0330131 U JPH0330131 U JP H0330131U JP 8971389 U JP8971389 U JP 8971389U JP 8971389 U JP8971389 U JP 8971389U JP H0330131 U JPH0330131 U JP H0330131U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- input
- comparison
- signal
- input signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003708 edge detection Methods 0.000 claims description 2
- 230000000630 rising effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Microcomputers (AREA)
Description
第１図は本考案の一実施例のマイクロコンピユ
ータのブロツク図である。
１……エツジ検出回路、２……カウンタ回路、
３……データ設定保持回路、４……比較回路、５
……入力制御回路、６……ＡＮＤゲートからなる
論理回路。
FIG. 1 is a block diagram of a microcomputer according to an embodiment of the present invention. 1...Edge detection circuit, 2...Counter circuit,
3... Data setting holding circuit, 4... Comparison circuit, 5
...Input control circuit, 6...Logic circuit consisting of AND gate.
Claims (1)
するエツジ検出回路と、前記入力信号の立上りも
しくは立下りエツジをトリガとして前記入力信号
のパルス幅を計測するカウンタ回路と、プログラ
ム命令により任意のデータが設定可能なデータ設
定保持回路と、前記カウンタ回路のカウント値と
前記データ設定保持回路の設定値とを比較する比
較回路と、前記比較回路の比較一致信号により制
御される入力制御回路と、前記入力信号の信号レ
ベルにより前記カウンタ回路に入力されるクロツ
クを制御する論理回路とを含む入力回路を設けた
ことを特徴とするマイクロコンピユータ。 An edge detection circuit that detects the rising or falling edge of an input signal, a counter circuit that measures the pulse width of the input signal using the rising or falling edge of the input signal as a trigger, and arbitrary data can be set by program instructions. a data setting holding circuit; a comparison circuit that compares the count value of the counter circuit with a setting value of the data setting holding circuit; an input control circuit controlled by a comparison match signal of the comparison circuit; A microcomputer comprising an input circuit including a logic circuit that controls a clock input to the counter circuit according to a signal level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8971389U JPH0330131U (en) | 1989-07-28 | 1989-07-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8971389U JPH0330131U (en) | 1989-07-28 | 1989-07-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0330131U true JPH0330131U (en) | 1991-03-25 |
Family
ID=31639282
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8971389U Pending JPH0330131U (en) | 1989-07-28 | 1989-07-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0330131U (en) |
-
1989
- 1989-07-28 JP JP8971389U patent/JPH0330131U/ja active Pending