JPS62133479U - - Google Patents

Info

Publication number
JPS62133479U
JPS62133479U JP2074986U JP2074986U JPS62133479U JP S62133479 U JPS62133479 U JP S62133479U JP 2074986 U JP2074986 U JP 2074986U JP 2074986 U JP2074986 U JP 2074986U JP S62133479 U JPS62133479 U JP S62133479U
Authority
JP
Japan
Prior art keywords
synchronization signal
input
terminal connected
circuit
input terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2074986U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP2074986U priority Critical patent/JPS62133479U/ja
Publication of JPS62133479U publication Critical patent/JPS62133479U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図ないし第3図は本考案の実施例を示すも
ので、第1図は同期信号の極性合わせ回路の回路
構成図、第2図は入力される同期信号が正極性の
場合の入出力信号のタイムチヤート、第3図は入
力される同期信号が負極性の場合の入出力信号の
タイムチヤート、第4図は従来の同期信号の極性
合わせ回路の回路構成図である。 1……同期信号の極性合わせ回路、2……排他
的論理和ゲート回路、10……積分回路、12…
…入力部。
Figures 1 to 3 show embodiments of the present invention. Figure 1 is a circuit configuration diagram of a synchronization signal polarity matching circuit, and Figure 2 is an input/output diagram when the input synchronization signal has positive polarity. FIG. 3 is a time chart of input/output signals when the input synchronizing signal is of negative polarity, and FIG. 4 is a circuit configuration diagram of a conventional synchronizing signal polarity matching circuit. 1... Synchronization signal polarity matching circuit, 2... Exclusive OR gate circuit, 10... Integrating circuit, 12...
...Input section.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 排他的論理和ゲート回路を備え、この排他的論
理和ゲート回路は、その一方の入力端子を積分回
路を介して同期信号の入力部に接続し、他方の入
力端子を前記同期信号の入力部に直結しているこ
とを特徴とする同期信号の極性合わせ回路。
The exclusive OR gate circuit has one input terminal connected to the input section of the synchronization signal via an integrating circuit, and the other input terminal connected to the input section of the synchronization signal. A synchronization signal polarity matching circuit characterized by direct connection.
JP2074986U 1986-02-14 1986-02-14 Pending JPS62133479U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2074986U JPS62133479U (en) 1986-02-14 1986-02-14

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2074986U JPS62133479U (en) 1986-02-14 1986-02-14

Publications (1)

Publication Number Publication Date
JPS62133479U true JPS62133479U (en) 1987-08-22

Family

ID=30816544

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2074986U Pending JPS62133479U (en) 1986-02-14 1986-02-14

Country Status (1)

Country Link
JP (1) JPS62133479U (en)

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