JPS6381565U - - Google Patents

Info

Publication number
JPS6381565U
JPS6381565U JP17631386U JP17631386U JPS6381565U JP S6381565 U JPS6381565 U JP S6381565U JP 17631386 U JP17631386 U JP 17631386U JP 17631386 U JP17631386 U JP 17631386U JP S6381565 U JPS6381565 U JP S6381565U
Authority
JP
Japan
Prior art keywords
vertical synchronization
shot multivibrator
delay
utility
respect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17631386U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP17631386U priority Critical patent/JPS6381565U/ja
Publication of JPS6381565U publication Critical patent/JPS6381565U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Synchronizing For Television (AREA)
  • Details Of Television Scanning (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例による垂直同期回
路を示すブロツク図、第2図は第1図の垂直同期
回路におけるタイミングチヤート、第3図は従来
の垂直同期回路のブロツク図、第4図は従来の垂
直同期回路におけるタイミングチヤートである。 図において、1はワンシヨツトマルチバイブレ
イター、2は垂直偏向回路を示す。なお、図中、
同一符号は同一、又は相当部分を示す。
Fig. 1 is a block diagram showing a vertical synchronous circuit according to an embodiment of this invention, Fig. 2 is a timing chart in the vertical synchronous circuit of Fig. 1, Fig. 3 is a block diagram of a conventional vertical synchronous circuit, and Fig. 4. is a timing chart in a conventional vertical synchronization circuit. In the figure, 1 is a one-shot multivibrator, and 2 is a vertical deflection circuit. In addition, in the figure,
The same reference numerals indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 垂直同期信号を映像信号に対して遅延させるた
めにワンシヨツトマルチバイブレータを用いた事
を特徴とする垂直同期回路。
A vertical synchronization circuit characterized by using a one-shot multivibrator to delay a vertical synchronization signal with respect to a video signal.
JP17631386U 1986-11-17 1986-11-17 Pending JPS6381565U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17631386U JPS6381565U (en) 1986-11-17 1986-11-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17631386U JPS6381565U (en) 1986-11-17 1986-11-17

Publications (1)

Publication Number Publication Date
JPS6381565U true JPS6381565U (en) 1988-05-28

Family

ID=31116438

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17631386U Pending JPS6381565U (en) 1986-11-17 1986-11-17

Country Status (1)

Country Link
JP (1) JPS6381565U (en)

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