JPH0345595U - - Google Patents
Info
- Publication number
- JPH0345595U JPH0345595U JP10740489U JP10740489U JPH0345595U JP H0345595 U JPH0345595 U JP H0345595U JP 10740489 U JP10740489 U JP 10740489U JP 10740489 U JP10740489 U JP 10740489U JP H0345595 U JPH0345595 U JP H0345595U
- Authority
- JP
- Japan
- Prior art keywords
- dot clock
- clock generation
- generation circuit
- circuit
- afc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Video Image Reproduction Devices For Color Tv Systems (AREA)
- Processing Of Color Television Signals (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Transforming Electric Information Into Light Information (AREA)
Description
第１図は本考案の実施例に係るドツトクロツク
生成回路のブロツク図、第２図は従来のドツトク
ロツク生成回路のブロツク図である。
１……ＣＲＴ表示用出力コネクタ、４……ＰＬ
Ｌ回路、１０……ＡＦＣ回路。
FIG. 1 is a block diagram of a dot clock generation circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional dot clock generation circuit. 1...Output connector for CRT display, 4...PL
L circuit, 10...AFC circuit.
Claims (1)
づいてドツトクロツクを発生するＰＬＬ回路を備
えたドツトクロツク生成回路において、 前記ＰＬＬ回路の水平同期信号の入力側前段に
自動周波数制御（ＡＦＣ）回路を設けたことを特
徴とするドツトクロツク生成回路。[Claims for Utility Model Registration] A dot clock generation circuit including a PLL circuit that generates a dot clock based on a horizontal synchronization signal included in a color television signal, wherein an automatic frequency control ( A dot clock generation circuit characterized by being provided with an AFC) circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10740489U JPH0345595U (en) | 1989-09-13 | 1989-09-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10740489U JPH0345595U (en) | 1989-09-13 | 1989-09-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0345595U true JPH0345595U (en) | 1991-04-26 |
Family
ID=31656097
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10740489U Pending JPH0345595U (en) | 1989-09-13 | 1989-09-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0345595U (en) |
-
1989
- 1989-09-13 JP JP10740489U patent/JPH0345595U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0324772U (en) | ||
| JPH0345595U (en) | ||
| JPH042177U (en) | ||
| JPS6040164U (en) | Display clock generation circuit | |
| JPS63114565U (en) | ||
| JPH0186373U (en) | ||
| JPS6221691U (en) | ||
| JPS61154071U (en) | ||
| JPS6381565U (en) | ||
| JPH0260373U (en) | ||
| JPS6315684U (en) | ||
| JPS6293863U (en) | ||
| JPS615066U (en) | Video display device | |
| JPH0282170U (en) | ||
| JPS6286775U (en) | ||
| JPH01137675U (en) | ||
| JPS6047369U (en) | horizontal deflection circuit | |
| JPS63192778U (en) | ||
| JPH02130176U (en) | ||
| JPS6411071U (en) | ||
| JPH0357676U (en) | ||
| JPS60119166U (en) | View finder | |
| JPS62114579U (en) | ||
| JPS63120479U (en) | ||
| JPH03114889U (en) |