JPH0282170U - - Google Patents
Info
- Publication number
- JPH0282170U JPH0282170U JP16145288U JP16145288U JPH0282170U JP H0282170 U JPH0282170 U JP H0282170U JP 16145288 U JP16145288 U JP 16145288U JP 16145288 U JP16145288 U JP 16145288U JP H0282170 U JPH0282170 U JP H0282170U
- Authority
- JP
- Japan
- Prior art keywords
- comparator
- circuit
- vertical synchronization
- terminal
- slice level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 230000010355 oscillation Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Landscapes
- Synchronizing For Television (AREA)
Description
第１図は、本考案の実施例、第２図、第３図は
従来の実施例、第４図は第３図の実施例の各ブロ
ツクの動作図、第５図は第３図の実施例に第５図
ａの非標準信号が入力された場合の各ブロツクの
動作図である。第６図、第７図は本考案の第１図
の動作図である。
１……同期分離回路、２……積分回路、３……
コンパレータ、４……垂直発振回路、５……同期
分離入力回路、６……スライスレベル設定端子、
７……ボリユウム、８……同期分離出力端子、９
……積分回路、１０……コンパレータ入力端子、
１１……水平同期信号、１２……垂直同期信号、
１３……積分波形、１４……コンパレータスライ
スレベル、１５……コンパレータ出力（垂直トリ
ガパルス）。
Fig. 1 shows an embodiment of the present invention, Figs. 2 and 3 show a conventional embodiment, Fig. 4 shows an operation diagram of each block in the embodiment of Fig. 3, and Fig. 5 shows an implementation of Fig. 3. FIG. 5 is a diagram illustrating the operation of each block when the non-standard signal shown in FIG. 5a is input as an example. 6 and 7 are operation diagrams of the present invention shown in FIG. 1. 1...Synchronization separation circuit, 2...Integrator circuit, 3...
Comparator, 4...Vertical oscillation circuit, 5...Synchronization separation input circuit, 6...Slice level setting terminal,
7... Volume, 8... Synchronous separation output terminal, 9
...Integrator circuit, 10...Comparator input terminal,
11...Horizontal synchronization signal, 12...Vertical synchronization signal,
13... Integral waveform, 14... Comparator slice level, 15... Comparator output (vertical trigger pulse).
Claims (1)
コンパレータ用のスライスレベル設定用の端子を
設けたことを特徴とする垂直同期回路。 1. A vertical synchronization circuit in an integrated circuit for television, characterized in that a terminal for setting a slice level for a comparator of the vertical synchronization circuit is provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16145288U JPH0282170U (en) | 1988-12-12 | 1988-12-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16145288U JPH0282170U (en) | 1988-12-12 | 1988-12-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0282170U true JPH0282170U (en) | 1990-06-25 |
Family
ID=31444402
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16145288U Pending JPH0282170U (en) | 1988-12-12 | 1988-12-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0282170U (en) |
-
1988
- 1988-12-12 JP JP16145288U patent/JPH0282170U/ja active Pending
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