JPS6226977U - - Google Patents
Info
- Publication number
- JPS6226977U JPS6226977U JP11654085U JP11654085U JPS6226977U JP S6226977 U JPS6226977 U JP S6226977U JP 11654085 U JP11654085 U JP 11654085U JP 11654085 U JP11654085 U JP 11654085U JP S6226977 U JPS6226977 U JP S6226977U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- frequency division
- horizontal
- signal
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001360 synchronised effect Effects 0.000 claims description 5
- 238000000926 separation method Methods 0.000 claims 4
- 230000010355 oscillation Effects 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Synchronizing For Television (AREA)
Description
第１図は本考案の一実施例に係る水平同期回路
のブロツク構成図、第２図は水平同期回路の各部
波形を示す信号波形図、第３図は従来の水平同期
回路のブロツク構成図を示す。
FIG. 1 is a block configuration diagram of a horizontal synchronous circuit according to an embodiment of the present invention, FIG. 2 is a signal waveform diagram showing waveforms of each part of the horizontal synchronous circuit, and FIG. 3 is a block configuration diagram of a conventional horizontal synchronous circuit. show.
Claims (1)
信号を分離する同期分離回路と、基準発振周波数
信号を設定される分周比に応じてカウントダウン
し水平発振出力とする可変分周回路と、前記水平
同期信号と水平発振出力との位相比較を行い比較
結果である誤差信号を前記分周比を可変制御する
ための制御信号として前記可変分周器に供給する
分周比制御手段とを有する水平同期回路において
前記同期分離回路の出力を積分する積分回路と、
前記積分回路の出力する積分値が所定値以下の場
合には、前記同期分離回路に供給されている前記
デジタルビデオ信号中の特定ビツトの値を所定の
値に固定し前記同期分離回路に供給する切換手段
とを具備したことを特徴とする水平同期回路。 a synchronization separation circuit that inputs a digital video signal and separates a horizontal synchronization signal from it; a variable frequency division circuit that counts down a reference oscillation frequency signal according to a set frequency division ratio and outputs the horizontal oscillation; and the horizontal synchronization signal. and horizontal oscillation output, and a frequency division ratio control means for supplying an error signal as a comparison result to the variable frequency divider as a control signal for variably controlling the frequency division ratio. an integrating circuit that integrates the output of the synchronous separation circuit;
If the integral value output from the integrating circuit is less than a predetermined value, the value of a specific bit in the digital video signal supplied to the sync separation circuit is fixed to a predetermined value, and the value is supplied to the sync separation circuit. A horizontal synchronous circuit characterized by comprising a switching means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11654085U JPH0540613Y2 (en) | 1985-07-31 | 1985-07-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11654085U JPH0540613Y2 (en) | 1985-07-31 | 1985-07-31 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6226977U true JPS6226977U (en) | 1987-02-18 |
| JPH0540613Y2 JPH0540613Y2 (en) | 1993-10-14 |
Family
ID=31001227
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11654085U Expired - Lifetime JPH0540613Y2 (en) | 1985-07-31 | 1985-07-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0540613Y2 (en) |
-
1985
- 1985-07-31 JP JP11654085U patent/JPH0540613Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0540613Y2 (en) | 1993-10-14 |
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