JPH0177070U - - Google Patents
Info
- Publication number
- JPH0177070U JPH0177070U JP1987173135U JP17313587U JPH0177070U JP H0177070 U JPH0177070 U JP H0177070U JP 1987173135 U JP1987173135 U JP 1987173135U JP 17313587 U JP17313587 U JP 17313587U JP H0177070 U JPH0177070 U JP H0177070U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- signal
- clock
- magnitude
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Synchronizing For Television (AREA)
- Television Systems (AREA)
Description
第１図は本考案のクロツク同期化回路の要部の
一実施例を示すブロツク図、第２図はそのクロツ
ク同期化回路全体の概略構成を示すブロツク図、
第３図はその要部の従来回路例を示すブロツク図
、第４図はＨＤ・ＴＶ信号の水平同期信号部の波
形図である。
８：乗算係数切換制御回路、９：可変係数乗算
器。
FIG. 1 is a block diagram showing an embodiment of the main part of the clock synchronization circuit of the present invention, and FIG. 2 is a block diagram showing a schematic configuration of the entire clock synchronization circuit.
FIG. 3 is a block diagram showing an example of a conventional circuit of the main part thereof, and FIG. 4 is a waveform diagram of a horizontal synchronizing signal section of an HD/TV signal. 8: Multiplication coefficient switching control circuit, 9: Variable coefficient multiplier.
Claims (1)
、多重サブサンプリング処理により帯域圧縮され
且つＡ／Ｄ変換された高品位テレビジヨン信号中
の水平同期信号部に同期させるためのクロツク同
期化回路に於いて、前記水平同期信号部と前記ク
ロツク信号の分周出力との位相を比較する位相比
較回路と、その比較出力によつて制御される前記
電圧制御発振器との間に可変係数乗算回路を設け
ると共に、前記水平同期信号部の振幅の大きさを
検出する検出回路を設け、この検出回路の出力に
応じて上記係数乗算回路にセツトする係数の大き
さを切換えるようにしたことを特徴とする高品位
テレビジヨン受像機のクロツク同期化回路。 In a clock synchronization circuit for synchronizing a clock signal generated from a voltage controlled oscillator with a horizontal synchronization signal portion in a high-definition television signal whose band has been compressed by multiple subsampling processing and A/D converted, A variable coefficient multiplication circuit is provided between a phase comparison circuit that compares the phase of the horizontal synchronization signal section and the frequency-divided output of the clock signal, and the voltage controlled oscillator that is controlled by the comparison output; A high-definition television set, comprising: a detection circuit for detecting the magnitude of the amplitude of a horizontal synchronizing signal section; and a magnitude of a coefficient set in the coefficient multiplication circuit is switched in accordance with the output of the detection circuit. Receiver clock synchronization circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987173135U JPH0177070U (en) | 1987-11-12 | 1987-11-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987173135U JPH0177070U (en) | 1987-11-12 | 1987-11-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0177070U true JPH0177070U (en) | 1989-05-24 |
Family
ID=31465071
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987173135U Pending JPH0177070U (en) | 1987-11-12 | 1987-11-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0177070U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05260339A (en) * | 1992-03-10 | 1993-10-08 | Fujitsu General Ltd | Digital pll circuit |
-
1987
- 1987-11-12 JP JP1987173135U patent/JPH0177070U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05260339A (en) * | 1992-03-10 | 1993-10-08 | Fujitsu General Ltd | Digital pll circuit |
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