JPS62161472U - - Google Patents
Info
- Publication number
- JPS62161472U JPS62161472U JP4955786U JP4955786U JPS62161472U JP S62161472 U JPS62161472 U JP S62161472U JP 4955786 U JP4955786 U JP 4955786U JP 4955786 U JP4955786 U JP 4955786U JP S62161472 U JPS62161472 U JP S62161472U
- Authority
- JP
- Japan
- Prior art keywords
- aft
- circuit
- output
- tuner
- fixed bias
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 238000000926 separation method Methods 0.000 claims description 3
- 239000000284 extract Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Television Receiver Circuits (AREA)
Description
第1図はこの考案の一実施例による選局回路の
ブロツク回路図、第2図は従来の選局回路を示す
ブロツク回路図である。
1…アンテナ、2…チユーナ、3…VIF出力
、4…VIF回路、5…ビデオ検波出力、7…A
FT出力、8…同期分離回路、9…水平同期パル
ス出力、10…選局用マイクロコンピユータ、1
1…チユーニング電圧、12…チユーナAFT入
力、13…AFT固定バイアス回路、14…ビデ
オ入力端子、16…スイツチ回路、17,18…
スイツチ。なお、図中、同一符号は同一または相
当部分を示す。
FIG. 1 is a block circuit diagram of a tuning circuit according to an embodiment of this invention, and FIG. 2 is a block circuit diagram showing a conventional tuning circuit. 1...Antenna, 2...Tuner, 3...VIF output, 4...VIF circuit, 5...Video detection output, 7...A
FT output, 8... Synchronization separation circuit, 9... Horizontal synchronization pulse output, 10... Microcomputer for channel selection, 1
DESCRIPTION OF SYMBOLS 1... Tuning voltage, 12... Tuner AFT input, 13... AFT fixed bias circuit, 14... Video input terminal, 16... Switch circuit, 17, 18...
Switch. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
、このチユーナから出力されるVIF出力にもと
づいてビデオ検波出力およびAFT出力を出すV
IF回路と、上記ビデオ検波出力または外部ビデ
オ入力から同期信号を取出す同期分離回路と、上
記AFT出力および上記同期分離回路から水平同
期パルス出力が供給され上記チユーナへチユーニ
ング電圧を出力する選局用マイクロコンピユータ
と、上記チユーナにAFT入力を与えるためのA
FT固定バイアス回路とを備えた選局回路におい
て、サーチモードにおいては上記AFT固定バイ
アス回路から上記チユーナにAFT固定バイアス
を、また選局用マイクロコンピユータにはVIF
回路からのAFT出力をそれぞれ供給する一方、
通常動作中においては選局用マイクロコンピユー
タにAFT固定バイアスを、またチユーナにはV
IF回路からのAFT出力をそれぞれ供給するよ
うに切り換え動作を行なうスイツチ回路を設けた
ことを特徴とする選局回路。 A tuner that selects a received signal from an antenna, and a V that outputs a video detection output and an AFT output based on the VIF output output from this tuner.
an IF circuit, a synchronization separation circuit that extracts a synchronization signal from the video detection output or external video input, and a tuning micro that receives horizontal synchronization pulse output from the AFT output and the synchronization separation circuit and outputs a tuning voltage to the tuner. A computer and an A for providing AFT input to the above tuner.
In the channel selection circuit equipped with an FT fixed bias circuit, in the search mode, the AFT fixed bias circuit applies an AFT fixed bias to the tuner, and the VIF is applied to the tuning microcomputer.
While supplying the AFT output from the circuit respectively,
During normal operation, AFT fixed bias is applied to the tuning microcomputer, and V is applied to the tuner.
A channel selection circuit comprising a switch circuit that performs a switching operation to supply AFT outputs from IF circuits.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4955786U JPS62161472U (en) | 1986-04-01 | 1986-04-01 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4955786U JPS62161472U (en) | 1986-04-01 | 1986-04-01 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62161472U true JPS62161472U (en) | 1987-10-14 |
Family
ID=30872118
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4955786U Pending JPS62161472U (en) | 1986-04-01 | 1986-04-01 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62161472U (en) |
-
1986
- 1986-04-01 JP JP4955786U patent/JPS62161472U/ja active Pending
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