JPS6172930U - - Google Patents
Info
- Publication number
- JPS6172930U JPS6172930U JP15902884U JP15902884U JPS6172930U JP S6172930 U JPS6172930 U JP S6172930U JP 15902884 U JP15902884 U JP 15902884U JP 15902884 U JP15902884 U JP 15902884U JP S6172930 U JPS6172930 U JP S6172930U
- Authority
- JP
- Japan
- Prior art keywords
- channel selection
- circuit
- skip
- channel
- video signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
Description
第１図は本考案に係る選局装置の概略を示す信
号ブロツク図、第２図は選局回路の構成図、第３
図は映像信号受信判別回路の構成図である。
１…チユーナ、３…映像信号受信判別回路、４
…選局回路、ｆ…スキツプ信号。
FIG. 1 is a signal block diagram showing an outline of the tuning device according to the present invention, FIG. 2 is a configuration diagram of the tuning circuit, and FIG.
The figure is a configuration diagram of a video signal reception determination circuit. 1... Tuner, 3... Video signal reception determination circuit, 4
...Tuning selection circuit, f...Skip signal.
Claims (1)
の操作により、各チヤンネルに対して予め設定さ
れたチユーナ制御電圧を順次切り変えることが可
能なチヤンネル選局回路４を具えた受像機の選局
装置に於て、選定されたチヤンネルに映像信号が
ないときにスキツプ信号ｆを発生する映像信号受
信判別回路３と、前記スキツプ信号ｆが入力され
ることにより選局をスキツプせしめるスキツプ回
路とが装備されていることを特徴とする受像機の
選局装置。 映像信号受信判別回路３は、ＦＴＺミユート
回路にスイツチングトランジスタ３１を接続して
なる実用新案登録請求の範囲第１項に記載の選局
装置。 チヤンネル選局回路４は、スキツプ回路が内
蔵された選局用ＩＣ−μＰＣ１３６２Ｃに対し、
チユーナ制御電圧設定回路４５を接続してなる実
用新案登録請求の範囲第１項又は第２項に記載の
選局装置。[Scope of utility model registration claim] Up switch 42 or down switch 43
With the operation of , the video signal is transmitted to the selected channel in the channel selection device of the receiver equipped with the channel selection circuit 4 which can sequentially change the preset tuner control voltage for each channel. A channel selection device for a television receiver characterized in that it is equipped with a video signal reception discrimination circuit 3 that generates a skip signal f when the skip signal f is not available, and a skip circuit that skips channel selection when the skip signal f is input. Device. The video signal reception determination circuit 3 is a channel selection device according to claim 1, which is a utility model registration, and is formed by connecting a switching transistor 31 to an FTZ mute circuit. The channel selection circuit 4 is a channel selection IC-μPC1362C with a built-in skip circuit.
A channel selection device according to claim 1 or 2, which is connected to a tuner control voltage setting circuit 45.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15902884U JPS6172930U (en) | 1984-10-19 | 1984-10-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15902884U JPS6172930U (en) | 1984-10-19 | 1984-10-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6172930U true JPS6172930U (en) | 1986-05-17 |
Family
ID=30716989
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15902884U Pending JPS6172930U (en) | 1984-10-19 | 1984-10-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6172930U (en) |
-
1984
- 1984-10-19 JP JP15902884U patent/JPS6172930U/ja active Pending
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