JPH0415368U - - Google Patents
Info
- Publication number
- JPH0415368U JPH0415368U JP1990054662U JP5466290U JPH0415368U JP H0415368 U JPH0415368 U JP H0415368U JP 1990054662 U JP1990054662 U JP 1990054662U JP 5466290 U JP5466290 U JP 5466290U JP H0415368 U JPH0415368 U JP H0415368U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- charging
- video signal
- discharging
- video
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 238000007599 discharging Methods 0.000 claims 4
- 238000010586 diagram Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Description
第１図は、この考案による映像ミユート回路の
一実施例を示す構成図、第２図ＡとＢは第１図の
実施例の動作を説明するためのコンデンサＣ１と
Ｃ２の電位を示す図、第３図は従来の映像ミユー
ト回路例を示す構成図である。
１……同期分離回路、２……ビデオ信号検出回
路、３……同期信号発生回路、４……映像ミユー
ト回路、５……マイコン、６……デコード回路。
FIG. 1 is a block diagram showing an embodiment of the video mute circuit according to this invention, and FIGS. 2A and B show the potentials of capacitors C 1 and C 2 to explain the operation of the embodiment of FIG. 1. 3 are block diagrams showing an example of a conventional video mute circuit. DESCRIPTION OF SYMBOLS 1...Synchronization separation circuit, 2...Video signal detection circuit, 3...Synchronization signal generation circuit, 4...Video mute circuit, 5...Microcomputer, 6...Decoding circuit.
Claims (1)
と、 前記ビデオ信号検出回路により検出された映像
信号の有無に応じて互いに逆の充放電動作をする
２つの充放電回路と、 前記２つの充放電回路のそれぞれ充放電電位を
入力する排他的論理和回路と、 前記排他的論理和回路の出力により映像ミユー
ト信号の出力を制御するスイツチング回路と、 を備えて成ることを特徴とする映像ミユート回路
。[Claims for Utility Model Registration] A video signal detection circuit that detects the presence or absence of a video signal; and two charging and discharging circuits that perform charging and discharging operations in opposite directions depending on the presence or absence of the video signal detected by the video signal detection circuit. and an exclusive OR circuit that inputs charging and discharging potentials of the two charging and discharging circuits, respectively, and a switching circuit that controls the output of the video mute signal based on the output of the exclusive OR circuit. Features a video mute circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990054662U JPH0415368U (en) | 1990-05-28 | 1990-05-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990054662U JPH0415368U (en) | 1990-05-28 | 1990-05-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0415368U true JPH0415368U (en) | 1992-02-07 |
Family
ID=31576924
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990054662U Pending JPH0415368U (en) | 1990-05-28 | 1990-05-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0415368U (en) |
-
1990
- 1990-05-28 JP JP1990054662U patent/JPH0415368U/ja active Pending
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