JPS6285053U - - Google Patents
Info
- Publication number
- JPS6285053U JPS6285053U JP17639785U JP17639785U JPS6285053U JP S6285053 U JPS6285053 U JP S6285053U JP 17639785 U JP17639785 U JP 17639785U JP 17639785 U JP17639785 U JP 17639785U JP S6285053 U JPS6285053 U JP S6285053U
- Authority
- JP
- Japan
- Prior art keywords
- composite video
- circuit
- horizontal
- signal
- video signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002131 composite material Substances 0.000 claims description 7
- 230000001934 delay Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Synchronizing For Television (AREA)
- Studio Circuits (AREA)
Description
第１図は本考案の一実施例の回路図、第２図は
ピクチヤー・イン・ピクチヤー（ＰＩＰ）ＴＶ受
像機の概略構成図、第３図は信号波形図であり、
第３図ＡはＴＶ信号、第３図Ｂは水平フライバツ
クパルス、第３図Ｃは外部機器からの複合映像信
号をそれぞれ示している。
１……水平位相ロツク回路、２……ＰＬＬ回路
、３……遅延回路。
FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a schematic configuration diagram of a picture-in-picture (PIP) TV receiver, and FIG. 3 is a signal waveform diagram.
3A shows a TV signal, FIG. 3B shows a horizontal flyback pulse, and FIG. 3C shows a composite video signal from an external device. 1...Horizontal phase lock circuit, 2...PLL circuit, 3...Delay circuit.
Claims (1)
めの複合映像信号の水平位相ロツク回路において
、 一方の複合映像信号から分離された水平同期信
号を、他方の複合映像信号から分離された水平同
期信号に位相ロツクするための遅延制御信号を出
力するＰＬＬ回路と、 このＰＬＬ回路からの遅延制御信号に基づいて
前記一方の複合映像信号を遅延させる遅延回路と
を備えることを特徴とする複合映像信号の水平位
相ロツク回路。[Claims for Utility Model Registration] In a composite video signal horizontal phase lock circuit for locking the horizontal phase of two composite video signals, a horizontal synchronizing signal separated from one composite video signal is used to lock the horizontal phase of the other composite video signal. a PLL circuit that outputs a delay control signal for phase-locking to a horizontal synchronization signal separated from the PLL circuit; and a delay circuit that delays the one composite video signal based on the delay control signal from the PLL circuit. Features a horizontal phase lock circuit for composite video signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17639785U JPS6285053U (en) | 1985-11-15 | 1985-11-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17639785U JPS6285053U (en) | 1985-11-15 | 1985-11-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6285053U true JPS6285053U (en) | 1987-05-30 |
Family
ID=31116602
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17639785U Pending JPS6285053U (en) | 1985-11-15 | 1985-11-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6285053U (en) |
-
1985
- 1985-11-15 JP JP17639785U patent/JPS6285053U/ja active Pending
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