JPS6454464U - - Google Patents
Info
- Publication number
- JPS6454464U JPS6454464U JP14944787U JP14944787U JPS6454464U JP S6454464 U JPS6454464 U JP S6454464U JP 14944787 U JP14944787 U JP 14944787U JP 14944787 U JP14944787 U JP 14944787U JP S6454464 U JPS6454464 U JP S6454464U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- setting
- sync signal
- switches
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000926 separation method Methods 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000001360 synchronised effect Effects 0.000 description 1
Landscapes
- Synchronizing For Television (AREA)
Description
第１図は、本考案によるデジタル同期信号分離
回路の一実施例を示すブロツク図、第２図は、第
１図に示す回路の動作を説明する波形図、第３図
は、従来のデジタル同期信号分離回路を示すブロ
ツク図である。
４……切換回路、５……設定回路、６……Ｄ／
Ａ変換回路、７……同期分離回路、８……モノマ
ルチバイブレーター、９……モノマルチバイブレ
ーター、１０……スイツチ回路。
FIG. 1 is a block diagram showing one embodiment of the digital synchronization signal separation circuit according to the present invention, FIG. 2 is a waveform diagram explaining the operation of the circuit shown in FIG. 1, and FIG. FIG. 2 is a block diagram showing a signal separation circuit. 4...Switching circuit, 5...Setting circuit, 6...D/
A conversion circuit, 7... synchronous separation circuit, 8... mono multivibrator, 9... mono multivibrator, 10... switch circuit.
Claims (1)
路と、該設定回路の出力と入力デジタルビデオ信
号とを切換選択する切換回路と、該切換回路の出
力をＤ／Ａ変換するＤ／Ａ変換回路と、該Ｄ／Ａ
変換回路の出力から同期信号を分離する同期信号
分離回路と、該同期信号分離回路の出力から映像
信号のタイミングを検出して前記切換回路を前記
設定回路の出力を選択するように切換えるタイミ
ング調整回路とを有するするデジタル同期信号分
離回路。 a setting circuit that outputs a preset digital signal, a switching circuit that switches and selects the output of the setting circuit and an input digital video signal, and a D/A conversion circuit that converts the output of the switching circuit from D/A; The D/A
a sync signal separation circuit that separates a sync signal from the output of the conversion circuit; and a timing adjustment circuit that detects the timing of a video signal from the output of the sync signal separation circuit and switches the switching circuit to select the output of the setting circuit. A digital synchronization signal separation circuit comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14944787U JPS6454464U (en) | 1987-09-30 | 1987-09-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14944787U JPS6454464U (en) | 1987-09-30 | 1987-09-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6454464U true JPS6454464U (en) | 1989-04-04 |
Family
ID=31421686
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14944787U Pending JPS6454464U (en) | 1987-09-30 | 1987-09-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6454464U (en) |
-
1987
- 1987-09-30 JP JP14944787U patent/JPS6454464U/ja active Pending