JPS63133777U - - Google Patents

Info

Publication number
JPS63133777U
JPS63133777U JP2466087U JP2466087U JPS63133777U JP S63133777 U JPS63133777 U JP S63133777U JP 2466087 U JP2466087 U JP 2466087U JP 2466087 U JP2466087 U JP 2466087U JP S63133777 U JPS63133777 U JP S63133777U
Authority
JP
Japan
Prior art keywords
signals
video cable
cable
video
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2466087U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP2466087U priority Critical patent/JPS63133777U/ja
Publication of JPS63133777U publication Critical patent/JPS63133777U/ja
Pending legal-status Critical Current

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  • Digital Computer Display Output (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案のビデオケーブルの構成図、第
2図は従来のビデオケーブルの位相補正回路図を
示す。 第1図において、1は表示信号出力回路、2は
ビデオケーブル、3はデイスプレイユニツト、4
と6は遅延素子、5と7はスイツチをそれぞれ示
す。
FIG. 1 shows a configuration diagram of a video cable of the present invention, and FIG. 2 shows a phase correction circuit diagram of a conventional video cable. In Figure 1, 1 is a display signal output circuit, 2 is a video cable, 3 is a display unit, and 4 is a display signal output circuit.
and 6 are delay elements, and 5 and 7 are switches, respectively.

Claims (1)

【実用新案登録請求の範囲】 デジタルビデオ信号と水平同期デジタル信号と
をそれぞれ出力する表示信号出力回路1と、前記
各信号をそれぞれ伝送するビデオケーブル2と、
該ビデオケーブル2から前記各信号を入力される
デイスプレイユニツト3とから構成されてなるデ
ジタルアドレス型デイスプレイにおいて、 前記ビデオケーブル2の前記両信号を伝送する
ケーブル毎に、前記各信号の遅延量を変化させる
スイツチを設けたことを特徴とするビデオケーブ
ル。
[Claims for Utility Model Registration] A display signal output circuit 1 that outputs a digital video signal and a horizontal synchronization digital signal, and a video cable 2 that transmits each of the signals,
In a digital address type display comprising a display unit 3 which receives each of the signals from the video cable 2, the amount of delay of each of the signals is varied for each cable that transmits the two signals of the video cable 2. A video cable characterized in that it is equipped with a switch.
JP2466087U 1987-02-20 1987-02-20 Pending JPS63133777U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2466087U JPS63133777U (en) 1987-02-20 1987-02-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2466087U JPS63133777U (en) 1987-02-20 1987-02-20

Publications (1)

Publication Number Publication Date
JPS63133777U true JPS63133777U (en) 1988-09-01

Family

ID=30824095

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2466087U Pending JPS63133777U (en) 1987-02-20 1987-02-20

Country Status (1)

Country Link
JP (1) JPS63133777U (en)

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