JPS63108284U

JPS63108284U -

Info

Publication number: JPS63108284U
Application number: JP19935486U
Authority: JP
Priority date: 1986-12-27
Filing date: 1986-12-27
Publication date: 1988-07-12

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例に係わるテレビジヨ
ン受像機のクロツク作成回路の構成を示すブロツ
ク図、第２図は第１図のインターリーブ検出回路
１４の構成を示すブロツク図である。１１……信号抽出部、１２……第１の位相ロツ
クループ（ＰＬＬ）、１３……第２の位相ロツク
ループ、１４……インターリーブ検出回路、１５
……セレクタ、２１……カウンタ、２２……フイ
ールド・カウンタ、２３……ウインドー回路。 FIG. 1 is a block diagram showing the configuration of a clock generation circuit for a television receiver according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of the interleave detection circuit 14 of FIG. 1. 11... Signal extractor, 12... First phase lock loop (PLL), 13... Second phase lock loop, 14... Interleave detection circuit, 15
...Selector, 21...Counter, 22...Field counter, 23...Window circuit.

Claims

[Claims for Utility Model Registration] A signal extraction unit that extracts a horizontal synchronization signal and a color burst signal from a composite video signal;
a first phase lock loop for creating a first system clock signal having a frequency twice the frequency of the extracted color burst signal; and a second phase lock loop for creating a second system clock signal having a frequency four times the frequency of the extracted color burst signal. checking whether the video signals included in the composite video signal have an interleaving relationship based on whether a frequency difference between the phase lock loop and the first and second system clock signals is within a predetermined range. , a selection output section that selectively outputs the first system clock signal if there is no interleaving relationship, and selectively outputs the second system clock signal if there is an interleaving relationship. A clock generation circuit for a television receiver, characterized in that: