JPS60177569U - Clock signal generation circuit for digital television receivers - Google Patents

Clock signal generation circuit for digital television receivers

Info

Publication number
JPS60177569U
JPS60177569U JP1984063723U JP6372384U JPS60177569U JP S60177569 U JPS60177569 U JP S60177569U JP 1984063723 U JP1984063723 U JP 1984063723U JP 6372384 U JP6372384 U JP 6372384U JP S60177569 U JPS60177569 U JP S60177569U
Authority
JP
Japan
Prior art keywords
signal
generation circuit
clock signal
signal generation
horizontal synchronization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1984063723U
Other languages
Japanese (ja)
Other versions
JPH039429Y2 (en
Inventor
秀行 林
Original Assignee
日本電気ホームエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気ホームエレクトロニクス株式会社 filed Critical 日本電気ホームエレクトロニクス株式会社
Priority to JP1984063723U priority Critical patent/JPS60177569U/en
Publication of JPS60177569U publication Critical patent/JPS60177569U/en
Application granted granted Critical
Publication of JPH039429Y2 publication Critical patent/JPH039429Y2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Synchronizing For Television (AREA)
  • Color Television Systems (AREA)
  • Processing Of Color Television Signals (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、本考案の一実施例の構成を示すブロック図で
ある。 ３・・・・・・第１の位相ロックループ、４・・・・・
・第２の位相ロックループ、８，９・・・・・・分周回
路、１０・・・・・・カラーキラー回路、１２，１４・
・・・・・手動選択信号、２０〜２４・・・・・・スイ
ッチ回路。FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. 3...First phase-locked loop, 4...
・Second phase lock loop, 8, 9... Frequency divider circuit, 10... Color killer circuit, 12, 14...
...Manual selection signal, 20-24...Switch circuit.

Claims (1)

【実用新案登録請求の範囲】 テレビジョン信号の色副搬送波周波数の整数倍の周波数
のサイプリングパルス及び水平同期信号を発生するクロ
ック信号発生回路において、−複合映像信号のカラーバ
ーストから前記サンプリング・パルス及び前記水平同期
信号を発生する第１の位相ロックループと、 複合映像信号の水平同期信号から前記サンプリング・パ
ルス及び前記水平同期信号を発生する第２の位相ロック
ループと、 前記第１、第２の位相ロックループで発生されるサンプ
リング・パルス及び水平同期信号の組の一方をディジタ
ル化すべきテレビジョン信号の種類に応じて選択的に出
力せしめる選択手段とを備えたことを特徴とするディジ
タル・テレビジョン受像機用クロック信号発生回路。[Claims for Utility Model Registration] In a clock signal generation circuit that generates a sipling pulse and a horizontal synchronization signal having a frequency that is an integral multiple of the color subcarrier frequency of a television signal, - the sampling pulse is generated from a color burst of a composite video signal; and a first phase-locked loop that generates the horizontal synchronization signal; a second phase-locked loop that generates the sampling pulse and the horizontal synchronization signal from the horizontal synchronization signal of a composite video signal; A digital television set comprising: a selection means for selectively outputting one of a set of a sampling pulse and a horizontal synchronizing signal generated in a phase-locked loop according to the type of television signal to be digitized. Clock signal generation circuit for John receiver.
JP1984063723U 1984-04-30 1984-04-30 Clock signal generation circuit for digital television receivers Granted JPS60177569U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984063723U JPS60177569U (en) 1984-04-30 1984-04-30 Clock signal generation circuit for digital television receivers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984063723U JPS60177569U (en) 1984-04-30 1984-04-30 Clock signal generation circuit for digital television receivers

Publications (2)

Publication Number Publication Date
JPS60177569U true JPS60177569U (en) 1985-11-26
JPH039429Y2 JPH039429Y2 (en) 1991-03-08

Family

ID=30594141

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984063723U Granted JPS60177569U (en) 1984-04-30 1984-04-30 Clock signal generation circuit for digital television receivers

Country Status (1)

Country Link
JP (1) JPS60177569U (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6480184A (en) * 1987-09-22 1989-03-27 Nippon Denki Home Electronics Clock switching circuit
JPS6489883A (en) * 1987-09-30 1989-04-05 Nippon Denki Home Electronics Television receiver
JPH08340549A (en) * 1996-07-15 1996-12-24 Hitachi Ltd Digital television signal processor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5220093A (en) * 1975-08-08 1977-02-15 Hitachi Ltd Apparatus for determination of turbidity

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5220093A (en) * 1975-08-08 1977-02-15 Hitachi Ltd Apparatus for determination of turbidity

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6480184A (en) * 1987-09-22 1989-03-27 Nippon Denki Home Electronics Clock switching circuit
JPS6489883A (en) * 1987-09-30 1989-04-05 Nippon Denki Home Electronics Television receiver
JPH08340549A (en) * 1996-07-15 1996-12-24 Hitachi Ltd Digital television signal processor

Also Published As

Publication number Publication date
JPH039429Y2 (en) 1991-03-08

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