JPS63108280U - - Google Patents
Info
- Publication number
- JPS63108280U JPS63108280U JP20264986U JP20264986U JPS63108280U JP S63108280 U JPS63108280 U JP S63108280U JP 20264986 U JP20264986 U JP 20264986U JP 20264986 U JP20264986 U JP 20264986U JP S63108280 U JPS63108280 U JP S63108280U
- Authority
- JP
- Japan
- Prior art keywords
- output
- horizontal synchronization
- signal
- circuit
- sample
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000926 separation method Methods 0.000 claims description 4
- 239000002131 composite material Substances 0.000 claims 1
- 239000000284 extract Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Processing Of Color Television Signals (AREA)
- Color Television Systems (AREA)
- Television Systems (AREA)
Description
第１図は本考案によるＰＬＬ回路の一実施例を
示すブロツク構成図、第２図は第１図ののこぎり
波発生回路４とサンプル・ホールド回路３の一具
体例を示す回路図、第３図は従来のアナログ方式
のＰＬＬ回路の一例を示すブロツク構成図、第４
図はデイジタル方式のＰＬＬ回路の一例を示すブ
ロツク構成図である。
２……水平同期分離回路、３……サンプル・ホ
ールド回路、４……のこぎり波発生回路、５……
ローパスフイルタ、６……電圧制御発振器、７，
９……出力端子、８……１／２分周器、１１……
デイジタル位相検出器、１２……ローパスフイル
タ、１３……加算器。
FIG. 1 is a block diagram showing an embodiment of the PLL circuit according to the present invention, FIG. 2 is a circuit diagram showing a specific example of the sawtooth wave generation circuit 4 and sample-and-hold circuit 3 shown in FIG. 1, and FIG. 4 is a block diagram showing an example of a conventional analog PLL circuit.
The figure is a block diagram showing an example of a digital PLL circuit. 2...Horizontal synchronization separation circuit, 3...Sample/hold circuit, 4...Sawtooth wave generation circuit, 5...
Low pass filter, 6... Voltage controlled oscillator, 7,
9...Output terminal, 8...1/2 frequency divider, 11...
Digital phase detector, 12... low pass filter, 13... adder.
Claims (1)
信号を取り出す水平同期分離回路と、この水平同
期分離回路からの水平同期信号がサンプル・ホー
ルド制御信号として入力されるサンプル・ホール
ド回路と、このサンプル・ホールド回路の出力が
供給される第１のローパスフイルタと、第１の所
定の周波数信号を出力する電圧制御発振器と、こ
の電圧制御発振器の出力が供給され、かつ第２の
所定の周波数信号を出力する分周器と、この分周
器の出力にもとづきのこぎり波信号を前記サンプ
ル・ホールド回路に供給するのこぎり波発生回路
と、前記水平同期分離回路からの水平同期信号と
前記分周器の出力にもとづく信号を入力し、両信
号の位相差を検出するデイジタル位相検出器と、
このデイジタル位相検出器の出力が供給される第
２のローパスフイルタと、前記第１のローパスフ
イルタの出力と第２のローパスフイルタの出力を
加算し、前記電圧制御発振器に供給する加算器と
を備えてなり、前記第１および第２の所定の周波
数信号が水平同期信号と位相がロツクするように
動作することを特徴とするＰＬＬ回路。 A horizontal synchronization separation circuit that extracts a horizontal synchronization signal from an NTSC composite video signal, a sample and hold circuit to which the horizontal synchronization signal from this horizontal synchronization separation circuit is input as a sample and hold control signal, and an output of this sample and hold circuit. a first low-pass filter to which is supplied, a voltage controlled oscillator which outputs a first predetermined frequency signal, and a frequency divider to which the output of the voltage controlled oscillator is supplied and which outputs a second predetermined frequency signal. and a sawtooth wave generation circuit that supplies a sawtooth wave signal based on the output of the frequency divider to the sample and hold circuit, and inputs a horizontal synchronization signal from the horizontal synchronization separation circuit and a signal based on the output of the frequency divider. and a digital phase detector that detects the phase difference between both signals.
a second low-pass filter to which the output of the digital phase detector is supplied; and an adder that adds the output of the first low-pass filter and the output of the second low-pass filter and supplies the sum to the voltage-controlled oscillator. A PLL circuit, characterized in that the PLL circuit operates so that the first and second predetermined frequency signals are locked in phase with a horizontal synchronization signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20264986U JPS63108280U (en) | 1986-12-29 | 1986-12-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20264986U JPS63108280U (en) | 1986-12-29 | 1986-12-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63108280U true JPS63108280U (en) | 1988-07-12 |
Family
ID=31167235
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20264986U Pending JPS63108280U (en) | 1986-12-29 | 1986-12-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63108280U (en) |
-
1986
- 1986-12-29 JP JP20264986U patent/JPS63108280U/ja active Pending
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