JPH0422575Y2 - - Google Patents

Description

[Detailed explanation of the idea] [Industrial application field]

The present invention relates to a PLL circuit.

[Conventional technology]

The configurations of conventional PLL circuits shown in FIGS. 1 and 2 are known. In FIG. 1, the output frequency fb of the voltage controlled oscillator 4 is 1/1 by the frequency divider 1.
The frequency is divided into N and compared with the reference frequency fa by a phase comparator (comparator) 2, and the output of the phase difference is passed through a low-pass filter 3 to extract the DC component, which controls the oscillation frequency of the voltage-controlled oscillator 4. be. Then, when the phase difference disappears, locking occurs and a lock synchronized with the reference frequency is obtained. Furthermore, in FIG. 2, a separate frequency divider 1' is provided when it is necessary to obtain a clock whose frequency is divided by 1/M, independent of the loop of the PLL circuit. However, in this case, does the obtained clock fb lock with respect to the reference frequency at the falling edge?
It is unclear whether the clock is locked at the rising edge, and this clock cannot be used in another digital circuit.

[Problem that the invention attempts to solve]

The present invention was developed based on the above circumstances, and aims to provide a PLL circuit in which a clock based on the output of a voltage controlled oscillator is always synchronized at the rising edge or falling edge with respect to the reference frequency.

[Means to solve the problem]

For this purpose, the present invention provides a PLL circuit in which the frequency of a voltage controlled oscillator is divided by 1/N by a 1/N frequency divider, and the output thereof is phase-compared with a reference frequency by a comparator. A 1/M frequency divider for dividing the frequency of the voltage controlled oscillator by 1/M is provided on the output side of the oscillator, and a 1/M frequency divider is provided between the comparator and the 1/N frequency divider. A latch circuit is provided which uses a frequency divided by 1/M as a clock, and the relationship between N of the 1/N frequency divider and M of the 1/M frequency divider is N≧M. It is characterized by the fact that

【Example】

Hereinafter, one embodiment of the present invention will be explained in detail with reference to FIG. In the figure, reference numeral 14 is a voltage controlled oscillator, whose frequency is 1/N by the frequency divider 11.
The frequency is divided into 1/M by a frequency divider 11'. The frequency divided by 1/N enters the comparator 12 via the latch circuit 15 and is compared in phase with the reference frequency fa. Then, the DC component of the phase difference is extracted through the low-pass filter 13 to control the voltage controlled oscillator 14. When the phase difference disappears, the voltage controlled oscillator 14 is locked at the reference frequency. In this case, the latch circuit 15 includes a frequency divider 1
The output signal of 1' is input as a clock.
This point will be explained with reference to FIGS. 3 and 4. FIG. 3 shows a conventional circuit in which when the PLL circuit is locked, fb may be synchronized at the rising edge, or may be synchronized at the falling edge. However, in FIG. 4 (this invention), the output of the latch circuit 15, that is, the signal compared with the reference frequency, is controlled so that it changes only at the rising edge of fb, so the PLL circuit only changes at the rising edge of fb. Lock. Here, in this embodiment, M=2, and the relationship with N above is N≧M. Although the above embodiment shows an example in which locking occurs at the rising edge of fb, it is of course possible to lock at the falling edge of fb.

[Effect of the idea]

As described in detail above, the present invention has the practical effect of being able to obtain a clock with a clear phase relative to the reference frequency from the PLL circuit, which can be used as a clock for another digital circuit. .

[Brief explanation of drawings]

Figure 1 is a block diagram showing a general example of a PLL circuit.
Fig. 2 is a block diagram of a conventional example in comparison with the present invention, Fig. 3 is a signal timing chart of the conventional example, Fig. 4 is a signal timing chart according to the present invention, and Fig. 5 is an implementation of the present invention. FIG. 2 is a block diagram showing an example. 11... Frequency divider, 12... Comparator, 13
...Low pass filter, 14...Voltage controlled oscillator, 15...Latch circuit, 11'... Frequency divider.

Claims (1)

[Claims for Utility Model Registration] In a PLL circuit configured such that the frequency of a voltage controlled oscillator is divided by 1/N by a 1/N frequency divider, and the output thereof is phase-compared with a reference frequency by a comparator, the voltage control A 1/M frequency divider for dividing the frequency of the voltage controlled oscillator by 1/M is provided on the output side of the oscillator, and between the comparator and the 1/N frequency divider,
A latch circuit is provided that uses the frequency divided by 1/M by the 1/M frequency divider as a clock, and N of the 1/N frequency divider and M of the 1/M frequency divider are provided. A PLL circuit characterized in that the relationship between N≧M.