JPH0294726A - Out of locking preventing circuit for pll circuit - Google Patents

Abstract

PURPOSE:To prevent occurrence of out of locking in the occurrence of a phase jump of an input clock by detecting the phase jump of the input clock so as to set a frequency division circuit for feedback specifically. CONSTITUTION:A phase jump detection circuit 4 monitors a phase difference between an input clock 5 and a feedback clock 7, outputs a set signal 8 to a frequency divider circuit 3 for feedback of a PLL circuit 2 if any phase jump takes place in the clock 5. Then the circuit 3 is set so that the phase of the clock 7 is in matching with the phase of the clock 5 and the occurrence of out of locking in the PLL circuit 2 in the occurrence of a phase jump in the input clock is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is useful for preventing loss of lock due to phase jumps of input clocks in a PLL circuit for creating a slave synchronization clock of a strongly coupled slave synchronizer. The present invention relates to a suitable lock release prevention circuit for a PLL circuit.

[Conventional technology]

"Conventional Strongly Coupled Dependent Synchronous Circuit: rk'LL Design and Practical Circuit" (Mychik (1983), p. 75).

As described in Item 76), this is a circuit that divides the output of the VCO and feeds it back, detects the phase difference with the input clock, and generates an output clock that is 7A-locked to the input clock. However, no consideration is given to the disturbance of the output clock that occurs when the input clock undergoes a phase jump.

[The problem that the invention attempts to solve]

The above conventional technology does not take into consideration the possibility of loss of lock due to a phase jump of the input clock, and if a phase jump of the input clock occurs, the lock will be lost, and until the lock is re-locked, the clock that is not synchronized with the input clock There was a problem with outputting .

The object of the present invention is to
The purpose of this invention is to obtain a stable output clock by preventing the clock from becoming unlocked.

([Means for Solving the Problem] The above object is to provide a circuit that detects a phase jump in the input clock, and when a phase jump occurs in the input clock, the feedback divider circuit is This is achieved by placing the cents so that the phases match.

[Effect]

The input clock phase jump detection circuit is connected to the input clock and PL.
The phase difference between the L circuit and the feedback clock is constantly monitored, and a set signal is output when the phase of the P input clock and the feedback clock changes due to a phase jump in the input clock. As a result, the feedback frequency divider circuit of the PLL circuit is set, the phase of the input clock of the phase jump Rf& and the feedback clock is corrected, and the Pl and L circuits do not lose lock.

〔Example〕

An embodiment of the present invention will be explained below with reference to FIG. 1st
The figure shows a strongly coupled dependent synchronous circuit according to the present invention. As is well known, the PLL circuit includes a phase comparator circuit 1, a low-pass filter 9.
It is composed of a voltage controlled oscillator 10 and a feedback frequency dividing circuit 3. The input clock phase jump detection circuit 4 constantly monitors the phase difference between the input clock 5 and the feedback clock 7, and when a phase jump occurs in the input clock 5, it creates a set signal 8, sets the feedback frequency divider circuit, and outputs the input clock 5. and the phase of the feedback clock should match. Therefore, the reaction of the output voltage of the phase comparator circuit 1 due to the phase jump of the input clock is suppressed.
Even if a phase jump occurs in the input clock, the PLL circuit will not lose lock.

〔Effect of the invention〕

According to the present invention, even if a phase jump occurs in the input clock, the PLL circuit is prevented from losing its lock, so that it has the effect of completely suppressing disturbances in the output clock.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a strongly coupled dependent synchronization circuit that creates an output clock from an input clock according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Phase comparison circuit, 2... Phase a cruise circuit, 5... Frequency divider circuit for feedback, 4... Input clock phase jump detection circuit, 5... Input clock,
6... Output clock 7, 7... Feedback clock, 8... Seito M number, 9... Low pass filter,
10...Voltage controlled oscillator. Japanese patent attorney Katsuo Ogawa

Claims (1)

[Claims] 1. The phase of the input clock is input to a phase-locked loop circuit consisting of a phase comparison circuit that compares the phases of the input clock and the feedback clock, a low-pass filter, a voltage-controlled oscillator, and a feedback frequency divider circuit that generates the feedback clock. and an input clock phase jump detection circuit that detects a phase jump in the input clock by monitoring the phase of the feedback clock, and when a phase jump occurs in the input clock, the feedback frequency dividing circuit 1. A lock loss prevention circuit for a PLL circuit, characterized in that the phase of the feedback clock is set to match the phase of the input clock.