JPH01175482A - Digital television receiver - Google Patents

Abstract

PURPOSE:To make compatible the flexibility of a line lock mode, the facilitation of a memory practical application, the stability of the clock of a burst lock mode and a low jitter characteristic by providing a selecting circuit to output selectively the loop filter output of a horizontal phase synchronizing circuit and the loop filter output of a color sub-carrier phase synchronizing circuit. CONSTITUTION:At the time of a VTR mode, an error signal smoothed by a selecting circuit 23 is added with a set value NfH/(2Fx) by an adder circuit 16 for setting a clock frequency as it is. At the time of the TV mode, the output of a loop filter 8 of a color sub-carrier PLL is selected by the selecting circuit 23 and added to the adder circuit 16. The selecting circuit 23 is provided so as to switch and output the loop filter output from the color sub-carrier PLL and the loop filter output from a horizontal PLL by the TV/VTR mode and thus, at the time of the standard TV signal, the burst lock mode is obtained, and the stable clock with a small quantity of the jitter can be reproduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a digital television receiver that performs demodulation of video signals of NTSO system, PAL system, etc. by digital signal processing. This relates to a method for reproducing the system clock in the case of a system clock.

Conventional technology In recent years, rapid advances in semiconductor technology have led to faster and larger capacity semiconductor integrated circuits.
Memory and the like are increasingly being used. NTSC
In the case of signal processing, processing is often performed using a clock synchronized with a frequency four times that of the burst l-signal because it facilitates color demodulation and Y/C separation. However, when processing non-standard signals such as VTR signals, or when storing images in a frame memory and performing two-dimensional image processing such as scan conversion, the line lock method in which sample points are arranged in a grid pattern is used. It is more advantageous to use the clock of

JP-A-52-86722, JP-A-61-1610
An example of a digital television receiver using a line-lock type clock is disclosed in Japanese Patent No. 92 and the like.

An example of a conventional digital television receiver will be described below with reference to the drawings.

FIG. 2 is a block diagram showing the main components of a conventional digital television receiver. In FIG. 2, 1 is an analog-to-digital (A/D) conversion circuit. 2 is a band pass filter, and 3 is an automatic color gain control (AGO) circuit which controls the burst amplitude to be constant. 4 is a color demodulation circuit using synchronous detection using a multiplier, 5 is a low-pass filter, 6 is a comb filter, 7 is a burst gate,
8 is a loop filter, 9 is an adder that adds the loop error and the setting value of the color subcarrier frequency, 1o is a division circuit to cancel the influence of clock fluctuation, and 1161\-7 is a color subcarrier frequency according to the given setting value. It is a digital oscillator circuit that generates a carrier wave, and is a digital phase-locked circuit (PLL).
). The above is the configuration of the color signal processing circuit.

t*12il: low pass filter, 13 is a synchronous separation circuit, 14 is a phase comparison circuit, 15 is a loop filter, 16 is an adder circuit that sets the clock frequency, 17 is a digital oscillation circuit, 18 is a stable clock for the digital oscillation circuit 17 19 is a digital-to-analog (D/A) converter circuit, 20 is an analog multiplier circuit that doubles the triangular wave output from the D/A converter circuit 19 to generate a clock, and the entire circuit supply a clock to

21 is a frequency dividing circuit. The above constitutes a horizontal PLL.

The operation of the digital television receiver configured as described above will be explained below.

First, a video signal digitized by the A/D conversion circuit 1 has high-frequency noise suppressed by a low-pass filter 12, and is compared at black level by a synchronization separation circuit 13 to separate composite synchronization signal components. This signal is phase-compared with a horizontal pulse obtained by dividing the clock frequency by N by the frequency dividing circuit 21, and the error signal component is filtered by the loop filter 15 with the horizontal period (H
) are smoothed. The smoothed error signal is converted to a set value NrH/(2!F)[ by the clock frequency setting adder circuit 16.
) is added. Here, N is the frequency division ratio of the frequency divider circuit 21, F
H is the horizontal frequency, Fx is the crystal oscillation frequency, and F
x is a higher frequency than NFH. The added value is given to the digital oscillation circuit 17, which outputs sawtooth wave data with a frequency of NFH/2.

This data is shaped into a triangular wave and converted into an analog triangular wave with the frequency of NFH by the D/A conversion circuit 19, and a clock with the frequency of NFH is reproduced by the analog multiplier circuit 20. The analog multiplier circuit 20 can be realized by using an analog PLL circuit, for example.

Problems to be Solved by the Invention However, in the above configuration in which the clock is formed by a horizontal PLL, the control range of the clock is as wide as ±7 in order to accommodate non-standard signals input from a VTR, etc. This results in a PLL with a high frequency division ratio, resulting in problems such as a decrease in clock stability and generation of jitter. Unfortunately, in the case of standard television signals, the clock control range was only about ±0.015%, and the results were inferior to burst lock, which had a high degree of phase comparison. As a result, there has been a problem in that the Y/C separation characteristics may deteriorate when a frame comb filter is configured.

In view of the above-mentioned problems, the present invention provides a digital television that can regenerate the clock using a horizontal PLL as before for non-standard signals such as VTR signals, and can regenerate the clock using a chrominance carrier PLL for standard TV signals. This is to provide a John receiver.

In order to solve the second problem, the digital television receiver of the present invention has a horizontal phase synchronization circuit and a color subcarrier phase synchronization circuit, both of which are constructed of digital circuits. It is equipped with a selection circuit that selectively outputs the loop filter output of the horizontal phase-locked circuit and the loop filter output of the color subcarrier phase-locked circuit. The loop filter output of the synchronization circuit is selected, and when the standard signal is input, the loop filter output of the color subcarrier phase synchronization circuit is selected.

Operation With the above configuration, when the horizontal phase synchronization circuit is not locked and when a non-standard signal is input, the loop filter output of the horizontal phase synchronization circuit is selected and the clock is regenerated in line lock mode.
When a standard signal is input, the loop filter output of the color subcarrier phase synchronization circuit is selected and the clock is regenerated in burst lock mode. As a result, the number of signal samples can be kept constant for each line by following non-standard signals such as VTR signals, and memory applications can be facilitated. In addition, it is in burst lock mode for standard signals, allowing generation of highly accurate clocks with little jitter.

10-7 Embodiment Hereinafter, a digital television receiver according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the main configuration of a digital television receiver according to an embodiment of the present invention. The same components as in FIG. 2 are given the same reference numerals. In Figure 1, 1a and 1b are analog digitals (A/D)
It is a conversion circuit. 2 is a band pass filter, and 3 is an automatic color gain control (ACC) circuit which controls the burst amplitude to be constant. 4 is a color demodulation circuit using synchronous detection using a multiplier, 5 is a low-pass filter, 6 is a comb filter,
7 is a burst gate, 8 is a loop filter, 9 is an adder that adds the loop error and the setting value of the color subcarrier frequency, 1
0 is a division circuit to cancel the influence of clock fluctuation, 1
1 is a digital generation circuit that generates a color subcarrier according to a given setting value, and is a digital phase locked circuit (PL).
L). The above is the configuration of the color signal processing circuit.

11...7 Still 12 is a low-pass filter, 13 is a synchronous separation circuit, 1
4 is a phase comparison circuit, 15 is a loop filter, 23 is a selection circuit that selects the loop filter output, 22 is a standard/non-standard (TV/VTR) detection circuit, 16 is an adder circuit that sets the clock frequency, and 17 is a digital oscillation circuit. 18 is a crystal oscillation circuit that supplies a stable clock to a digital oscillation circuit, 19 is a digital-to-analog (D/A) conversion circuit, and 20 is an analog multiplier circuit, which is the D/A conversion circuit 19.
Generate a clock by doubling the triangular wave output from
Supplies all circuits. 21 is a frequency dividing circuit.

The above constitutes a horizontal phase locked loop (PLL).

The operation of the digital television receiver of this embodiment configured as described above will be explained below.

First, the video signal digitized by the A/D conversion circuit 1b has high-frequency noise suppressed by the low-pass filter 12, and is compared at black level by the synchronization separation circuit 13 to separate composite synchronization signal components.

This signal is phase-compared with a horizontal pulse obtained by dividing the clock frequency by N by the frequency dividing circuit 21, and the error signal component thereof is smoothed by the loop filter 15 every horizontal period (H).

In the VTR mode, the error signal smoothed by the selection circuit 23 is directly added to the set value NrH/(2F!) by the clock frequency setting adding circuit 16. Here N
is the frequency division ratio of the frequency dividing circuit 21, FH is the horizontal frequency, and Fx is the crystal oscillation frequency, and FX is a higher frequency than NFH.

In the TV mode, the output of the loop filter 8 of the color subcarrier PLL is selected by the selection circuit 23, and the output of the loop filter 8 of the color subcarrier PLL is selected by the selection circuit 23.
will be added to. In this adder circuit 16, the added value is given to a digital oscillation circuit 17, which outputs sawtooth wave data with a frequency of NFH/2. This data is shaped into a triangular wave and converted into an analog triangular wave with a frequency of NFH/2 by the D/A converter circuit 19, and a clock with a frequency of NFH is reproduced by the analog multiplier circuit 20. The analog multiplier circuit 20 uses, for example, an analog PLL circuit 13
, 5 This can be achieved by doing the following.

As described above, according to this embodiment, the selection circuit 23 is
By providing the VTR mode to switch between the loop filter output from the color subcarrier PLL and the loop filter output from the horizontal PLL, standard TV
When the signal is doubled, it can be set to burst lock mode and a stable clock with less jitter can be regenerated.

By taking advantage of the fact that both the horizontal PLL and color subcarrier PLL are composed of digital circuits, it is possible to measure standard/non-standard (TV/VTR) error and fluctuation components of each loop filter output. The mode can be determined, TV/V
By connecting the output of the TR detection circuit 22 to the control input of the selection circuit 23, the clock can be automatically switched.

Note that although the clock frequency and the like are not particularly defined in the above embodiment, these are very flexible and can be determined freely. - For example, the clock frequency is 13
．． 5MH2, frequency division ratio N==858.14, -.

The crystal oscillation frequency is 24.576 MHz, and as another example, the clock frequency is 14.31818MllZ,
Frequency division ratio N: 910, crystal oscillation frequency 28.63636M
It is jlz.

Effects of the Invention According to the present invention, by taking advantage of the fact that both the horizontal phase synchronization circuit and the color subcarrier phase synchronization circuit are configured with digital circuits, the loop filter output of the horizontal phase synchronization circuit and the color subcarrier phase synchronization circuit can be synchronized. By providing a selection circuit that selectively outputs the loop filter output, when the horizontal phase synchronization circuit is not locked or a non-standard signal is input, the loop filter output of the horizontal phase synchronization circuit is selected and the clock is regenerated in line lock mode, and the standard When inputting a signal, the loop filter output of the color subcarrier phase synchronization circuit is selected and the clock is regenerated in burst lock mode.The flexibility of line lock mode, the ease of memory application, and the stability of the clock in burst lock mode are provided. It is possible to achieve both low jitter characteristics and low jitter characteristics.

[Brief Description of the Drawings] Fig. 1 is a block diagram showing the main structure of a digital television receiver according to an embodiment of the present invention, and Fig. 2 is a block diagram showing the main structure of a conventional digital television receiver. be. 1... A/D conversion circuit, 4... Color posttone circuit, 7
・Burst Kate, 8・ ・Loop filter, 1Q ・
...Divider circuit, 11...Digital oscillation circuit, 1
3... Synchronization separation circuit, 14... Phase comparison circuit,
15... Loop filter, 17... Digital oscillation circuit, 20... Analog multiplier circuit, 22...
Standard/non-standard detection circuit, 23... selection circuit.

Claims (3)

[Claims] (1) An analog/digital converter that samples and quantizes the input video signal, and converts the quantized video signal into an integer horizontal synchronization signal using a horizontal phase synchronization circuit including at least a first loop filter and a digital oscillation circuit. A color subcarrier phase synchronization circuit including a clock regeneration device that regenerates at least one clock synchronized with a double frequency and at least a second loop filter that operates with the clock regenerates the color subcarrier, and color demodulation is performed by synchronous detection. a selection circuit that selectively outputs a loop filter output and a second loop filter output of the color subcarrier phase-locked circuit between the first loop filter of the horizontal phase-locked circuit and the digital oscillation circuit; When the horizontal phase synchronization circuit is unlocked and a non-standard signal is input, the first loop filter output of the horizontal phase synchronization circuit is selected and the clock is regenerated in line lock mode, and when the standard signal is input, the color subcarrier phase synchronization circuit is selected. A digital television receiver characterized in that a clock is recovered in a burst lock mode by selecting the second loop filter output of the digital television receiver. (2) a low-pass filter that suppresses high-frequency noise of the quantized video signal, and a sync separation circuit that separates the sync signal;
A frequency dividing circuit that divides the clock frequency and outputs a horizontal pulse, a phase comparison circuit that compares the phase of the horizontal synchronizing signal and the horizontal pulse, a first loop filter, and selects outputs of the first and second loop filters. a first addition circuit that sets the clock frequency; a digital oscillation circuit whose oscillation frequency is controlled by the input value; a crystal oscillation circuit that supplies a stable clock to the digital oscillation circuit; It is equipped with a digital/analog converter circuit that converts the output of the circuit from digital to analog, and an analog multiplier circuit that multiplies the output of the digital/analog converter circuit, and uses the output of the analog multiplier circuit as a line lock mode clock to convert the horizontal phase. A clock regeneration device that constitutes a synchronization circuit, a bandpass filter that extracts color signal components from a quantized video signal, and a color demodulation device that performs color demodulation using digitally regenerated color subcarriers and synchronous detection using a multiplier. a circuit, a low-pass filter that suppresses high-frequency components of the demodulated color signal, a burst gate that extracts the burst signal from the demodulated color difference signal, a second loop filter, and a second addition that sets the color subcarrier frequency. a color subcarrier circuit, a divider circuit that divides the output of the second adder circuit by the frequency control data of the horizontal phase synchronization circuit, and a digital oscillator circuit that digitally generates a color subcarrier according to a set value. 2. The digital television receiver according to claim 1, further comprising a color signal processing device that performs color demodulation using a carrier phase synchronization circuit. (3) It is characterized by being equipped with a standard/non-standard detection device that detects whether the signal is a standard signal or a non-standard signal from each loop filter output of the color subcarrier phase synchronization circuit and the horizontal phase synchronization circuit and automatically switches the selection circuit. A digital television receiver according to claim 1.