JPS62230286A - Digital television receiver - Google Patents

Abstract

PURPOSE:To obtain a broad-band brightness signal by orthoyonally modulating a demodulated color difference signal again, and subtracting it from a composite video signal. CONSTITUTION:A composite video signal 1 is inputted to an A/D converter 2 and digitized. The digitized composite video signal 3 is color-demodulated by a color signal processing circuit 100, and color difference signals 6 and 7 are outputted to a D/A converter 60. On the other hand, the color difference signals 8 and 9 taken out from a comb line filter 105 in the circuit 100 are inputted to a re-modulation circuit 200 where a color difference signal coming through a low-pass-filter 201 is orthoyonally modulated again by a orthoyonal conversion circuit 202 by using a color subcarrier wave, and subjected to an inverse ACC circuit 203, to be outputted as a carrier color signal 4. This signal 4 is subtracted, by a subtractor 302, from a composite video signal that underwent a delay circuit 301. Thus a brightness signal 5 is obtained, which is subjected to a brightness signal processing circuit 300, and outputted to a D/A converter 80.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a digital television receiver that performs demodulation of NTSC or PAL video signals through digital processing, and particularly relates to a method for separating luminance signals. be.

Background of the Invention In recent years, rapid advances in semiconductor technology have resulted in semiconductor integrated circuits becoming faster and larger in capacity, resulting in the production of audio signals.

Even analog signals such as video signals are now being processed by digital LSIs.

In the near future, video signal processing inside color televisions,
Synchronous signal processing and the like are being put into practical use. Most of them perform processing by synchronizing the clock at four times the burst rate, and have the advantage of easy demodulation of the color signal, but have the disadvantage that sampling of the synchronized signal is asynchronous, making processing complicated.

Here, we will discuss JP-A-52-867'2, which is relatively close to the present invention.
A conventional example will be explained using Publication No. 2 as an example.

FIG. 5 is a block diagram showing the configuration of a conventional example.

1 is an input composite video signal, which is converted into a digital signal by an analog/digital converter (hereinafter referred to as A/D converter) 2.
Carrier color signal 4 whose luminance signal is suppressed by converted bandpass filter B P □F10 and comb filter 11
is obtained, and by subtracting it from the original composite video signal 3 by the subtractor 12, a luminance signal Y5 is obtained. This configuration is the same as that of a conventional comb filter using a glass delay line. The sampling frequency of the A/D converter is selected to be m/n (m, n is an integer) of the color subcarrier frequency fsc. Further, if the horizontal synchronization frequency is fH, this relationship becomes 455.m-rll/2.n.

In the figure, 24 is a synchronous circuit, 23 is a voltage controlled oscillator, which is a circuit for generating a sampling pulse (clock) having the above relationship, and 22 is a variable phase shifter for changing the phase of the sampling pulse. It is.

The color subcarrier generator includes an address generator 19 and a ROM 20 .
Consists of 21. In order to control the phase of this color subcarrier, the color difference signal B-Y7 from which high-frequency components have been removed by a pass filter 15 is subjected to multiplicative detection in a multiplier 13, and is sampled only during the burst period by a burst gate 16. It is integrated and guided to a judgment circuit 18 to judge the direction and magnitude of the phase shift, and the judgment result is sent to an address generator 19 and a variable phase shifter 22.
The feed hack is performed to control the deviation to zero. The address generator corrects large deviations of more than one period of the sampling pulse, and the variable phase shifter provides small phase control. Color demodulation is performed by such synchronous sampling.
゛Problems to be Solved by the Invention The above configuration is fine when the horizontal synchronization frequency and the color subcarrier frequency are in an accurate interleaving relationship, as in television broadcasting, and the horizontal synchronization is very stable, but in VTR Since non-normal signals are not interleaved, synchronous sampling cannot be performed and stable color demodulation cannot be performed. Furthermore, if there is jitter in water type synchronization such as in a VTR, the sampling pulse will also have jitter, making the above configuration unstable. Further, although a regular luminance signal is fine, a non-regular signal may cause problems such as insufficient color signal suppression characteristics and leakage of the carrier color signal.

In view of the above points, the present invention enables stable color demodulation even for non-standard signals such as VTRs with a clock synchronized with the horizontal synchronization signal, and the luminance signal separation characteristics are also applicable to both regular and non-standard signals. The present invention provides a digital television receiver having a luminance signal separation circuit which automatically adopts a comb characteristic in the case of a regular signal and a trap characteristic in the case of a non-regular signal.

Further, the present invention provides a digital television receiver capable of demodulating orthogonally modulated television systems around the world such as NTSC' and PAL at the same clock frequency.

Furthermore, the present invention provides a digital television receiver that can obtain grid-like sampling point data at the same clock frequency and share image memory for television curve systems around the world.

Means for Solving the Problems In order to solve the above problems, the present invention includes an A/D converter that samples and quantizes an input composite video signal, and horizontal phase synchronization from the quantized composite video signal. a synchronous signal processing circuit that generates at least one clock reference signal by a loop; a clock generation circuit that generates at least -7 clock signals in synchronization with the daily basic signal; A color signal processing circuit that performs color demodulation using an operating digital phase-locked loop, a remodulation circuit that orthogonally modulates the demodulated color difference signal again, and a delay circuit and difference calculation circuit that performs delay correction on the quantized composite video signal. and is configured to separate the luminance signal by subtracting the remodulated carrier color signal from the composite video signal.

With the above configuration, a carrier color signal with the same phase and delay time can be obtained even in the case of a non-normal input signal, and by subtracting it from the original composite video signal, a normal or non-normal signal can be obtained. The luminance signal can be separated regardless of the In the case of a normal signal, the chrominance signal components are distributed in a comb shape with a horizontal frequency fH interval by a comb filter, and are further modulated by the chrominance subcarrier, resulting in a carrier chrominance signal interleaved with the luminance signal. Even after subtraction from the composite video signal, the luminance signal in the color signal band remains, and a luminance signal with an expanded band is obtained. Also, since sampling and signal processing are performed using a clock synchronized with the horizontal synchronization signal, VT
Even for non-normal signals such as R, the image sampling points are in a lattice pattern, and distortion-free images can be stored in the image memory.The digital phase-locked loop color demodulation circuit allows orthogonally modulated color signals from all over the world to be stored in the image memory. Since demodulation becomes possible and the clock frequency can be made the same for all television systems, the image memory can be shared.

Embodiment Hereinafter, a digital television receiver according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the main configuration of a digital television receiver in an embodiment of the present invention. Television waves received by an antenna are input to an A/D converter 2 as a composite video signal 1 via a tuner and a VIP. The digitized composite video signal 3 is sent to a color signal processing circuit 100.
The color difference signals 6 and 7 are color demodulated and output to the D/A converter 60.

The main signal flow in the color signal processing circuit 100 is through an ACC circuit 1 (including a bandpass filter BPFIOI and a shifter).
102), a color demodulation circuit 103 that reproduces color subcarriers using a digital phase-locked loop and performs color demodulation, a low-pass filter LPF 104, a comb filter 105 using an IH (horizontal synchronization) memory, and an ACC circuit including a multiplier. 2 (106). A color difference signal 8.9 is output from the output of the comb filter 105 to the remodulation circuit 200, and the ACC
The output of circuit 2 (106) is a color difference signal of 6.7.

Next, the remodulation circuit 200 outputs the subsampled color difference signal 8.
.
1 and an inverse ACC circuit 203 for inversely correcting the gain of the ACC circuit 1 (102) and reproducing the original carrier color signal 4.

In the luminance signal system, in order to correct the delay time in the color signal processing circuit 100 and the remodulation circuit 200, the composite video signal 3 first passes through the delay circuit 301, and then is converted into the carrier color signal 4 by the subtracter 302.
is subtracted to obtain a luminance signal 5, which is further subjected to processing such as horizontal and vertical aperture correction by the luminance signal processing circuit 300, and outputted to the D/A converter 80 as a luminance signal Y50.

The matrix circuit 70 generates primary color signals R, G, and B for driving the CRT 99 from the color difference signal from the D/A converter 60 and the luminance signal from the D/A converter 80.

On the other hand, the synchronization signal processing circuit 400 generates a clock reference signal 41 from the composite video signal 3 using a horizontal phase-locked loop, and also generates a horizontal drive pulse H42 and a vertical drive pulse V43 for driving the horizontal deflection and vertical deflection of the CRT. Output. The output circuit 90 receives these drive pulses and drives the deflection coil of the CRT.

The clock generation circuit 40 generates a clock from the clock reference signal 41 from the synchronous signal processing circuit by using an analog phase-locked loop or by multiplying it, and generates a clock from the clock reference signal 41 from the synchronous signal processing circuit. The signal is supplied to the luminance signal processing circuit 300, the synchronization signal processing circuit 400, etc.

Next, the internal configuration and operation of the synchronization signal processing circuit 400 will be explained in more detail.

FIG. 2 is a block diagram showing the internal configuration of the synchronization signal processing circuit 400, including some external circuits. The horizontal phase synchronization circuit 401 surrounded by a broken line in FIG. 2 is the main part of the synchronization signal processing circuit, and together with the external A/D converter 2 and the clock generation circuit 40, generates a clock synchronized with a frequency that is an integral multiple of the horizontal synchronization signal. generated and samples the input composite video signal.

First, when the power is turned on, the crystal oscillation circuit 410 oscillates and supplies a crystal clock (frequency Fx) to the digital oscillation circuit 407, and the digital oscillation circuit generates the clock reference frequency NFH/2 (for example, N
= 858, it oscillates near 6.75 MHz) and outputs a triangular wave signal 41 through the D/A converter 40B. This triangular wave signal 41 is multiplied by, for example, 2 by the clock generation circuit 40 and output to NFH (for example, 13.5 MHz when N=858).
clock is supplied to the entire system. A/D converter 2
In the composite video signal 3 converted into a digital value, a high-frequency carrier color signal component is suppressed by a low-pass filter LPF 402, and a luminance signal is canted by comparison with the black level in a synchronization separation circuit 403, and the peak value of the synchronization signal is detected. The synchronization signal is separated by comparing the two values. This synchronization signal is phase-compared with a horizontal pulse obtained by dividing the clock frequency by N by a frequency dividing circuit 409 in a phase comparator circuit 404, and the error component is filtered out by a loop filter 405 for one horizontal period I.
] is integrated and smoothed. The smoothed error signal is converted to the clock reference frequency setting value NF, , /2Fx by the adder 406.
and is added to the digital oscillation circuit 407.

In this way, the phase error is subjected to feedbank control and converges toward zero. When the phase error reaches a number of clocks, the phase comparator circuit 404 switches to a more precise one using the slope of the horizontal synchronization signal, and finally the horizontal synchronization signal and clock converge to a number of seconds. In this way, the horizontal synchronization signal and hence the luminance signal are sampled in a grid pattern with an accuracy of several nanoseconds, so the horizontal pulse 46 output from the frequency dividing circuit has little jitter and can be used as a horizontal drive pulse. . The output signal lNC45 from the adder 406 is a correction signal to the color demodulation circuit.

In an actual application example, it is necessary to absorb the effects of changes in the storage time of the transistor in the horizontal output circuit 91 of the television receiver and changes in the beam current of the CRT. Including the horizontal output circuit, 42 loops (second horizontal phase-locked loops) are configured. The output signal 42 of the variable delay circuit 413 is a horizontal drive pulse, and the output signal 42 of the variable delay circuit 413 is a horizontal drive pulse.
The input signal 47 to is the horizontal retrace pulse from the horizontal output circuit.

The synchronization signal processing circuit 400 further includes vertical synchronization related circuits. The synchronization signal that has passed through the low-pass filter 402 and further has its luminance signal cut is sent to the vertical synchronization separation circuit 402.
A low-pass filter is further applied at 0, and a vertical synchronization signal is obtained by comparing with the slice level. The vertical synchronization signal drives the vertical oscillation circuit 421 to generate vertical sawtooth data. This data is operated on by a vertical waveform generation circuit 422, and further converted into an analog signal by a D/A converter 423 to output a vertical sawtooth wave and a vertical parabolic wave. These signals are used by a vertical output circuit to drive a deflection coil or to correct pink distortion.

The operation of the above synchronization signal processing circuit is based on NTSC system, PAL system,
This is possible regardless of the SECAM method. The points to correspond to are the horizontal frequency (15,734kHz, 15.
625 k+Iz) and vertical frequency (60Hz.

50Hz) and can be easily supported 1 For example, for NTSC system N = 858, for PAL and SECAM system N =
864, the center frequency of the clock is 1 in any case.
3 and 5 Mllz, which can be handled by one clock generator. At this time, the degree of freedom of the crystal oscillation frequency FX is quite high, and it may be any value of about 20 to 30 MIIz, but for example, if FX = 24.576 MHz, the adder 4
The clock reference frequency setting value given to 07 is 6.75/2
4.576 = 0.274658, and in order to follow the clock with sufficient accuracy to the periodic change of the horizontal synchronization signal, the number of bits of the digital oscillation circuit needs to be, for example, 20 bits, and the addition of the 20 bit length is 24, 576
M1(z) must be used, but this can be accomplished by pipeline processing.

Next, the color signal processing circuit 100 and the remodulation circuit B200 will be explained according to FIG.

FIG. 3 is a block diagram showing the configurations of the color signal processing circuit 100 and the remodulation circuit 200.

The quantized composite video signal 3 is passed through a bandpass filter BP.
The carrier color signal component is extracted by the FIOI, and then the signal in the wide range is roughly adjusted by the chic 102. This ACC (automatic color amplitude adjustment) operation is performed by the shifter 102 and the subsequent multiplier 106 using control symbols from the ACC detection circuit. It is convenient to put the coefficients necessary to maintain a constant amplitude in the form of an exponent and a mantissa of a power of two. In other words, by setting the required multiplication coefficient to K and *2'' (1≦, <2), it is possible to have a control range of about 30 dB by multiplying the shift.

By separating the signals and inserting color demodulation between them in this way, reverse gain correction at the time of remodulation can be performed only by reverse shifting.

When passing through shifter 102, it is doubled to increase the accuracy of the burst. This sets the control signal to 1 only during the burst period.
This can be done by adding and shifting to the double side. The carrier color signal that has passed through shifter 102 is passed through multiplier 109. A baseband component and a 2fsc component appear through synchronous detection with orthogonal color subcarriers by ixo. The 2fsc component is suppressed by a low-pass filter 104, and the luminance signal component is canceled by a comb filter 165 having an IH memory. At this time, since the color difference signal at the output of the low-pass filter is sufficiently band-limited, it is possible to perform subsampling to lower the sampling frequency and reduce the number of delay stages of the IH memory. For example, if you drop it to A, the number of memory delay stages can be 2. Note that the comb filter is bypassed because the burst signal is used for PAL identification etc. at a later stage. Output signal of comb filter 1058.
9 is controlled to a constant amplitude burst by a multiplier 106 and outputs a color difference signal 6.7 through a color killer and pulse inch 107. The ACC detection circuit 108 extracts the burst period of the output color difference signal 53, 54 from the multiplier 106, compares it with an ACC reference value, and outputs an ACC control signal 5152.

The ACC control signal 51 is on the MSB side, and 52 is on the LSB side. The ACC detection circuit also has F A 1. , identification, and color killer detection are also performed, and the color killer and pulse switch 107 are controlled by the control symbol 55.

The color demodulation circuit 103 includes a burst gate 111, a loop filter 112, an adder 113 that adds the color subcarrier frequency setting value Fsc/FX, a divider 114, a digital oscillation circuit 115, an STN and CO3ROM 116, and multipliers 109 and 110. Consists of. The demodulated and gain-adjusted color difference signal (R'-Y) 53 burst period is accumulated by the burst gate 111 and averaged with the value before IH (this is necessary in the case of PAL), and the loop filter 112 Integrate and smooth for each IH, color subcarrier setting value FSC/FX
are added by an adder 113.

A divider 114 divides this result by the TNC signal 45 containing the phase error from the horizontal phase synchronization circuit. The reason for this is that the operating clock is generated from a horizontal phase synchronization circuit, so the clock follows fluctuations in the input horizontal synchronization signal.
This is to correct changes in the color subcarrier Fsc.

The digital oscillation circuit 115 has a configuration similar to an integrating circuit, and input data is accumulated every clock, and overflow is ignored, so that triangular wave data having a frequency proportional to the input data and the clock is output. In this case, the result of division is 2 F sc /N F I+, so if we further divide by 2, we get Fsc/NF)I.

Since NFH is a clock frequency, it is canceled by the digital oscillation circuit 115, and even if the clock frequency fluctuates, the digital oscillation circuit 115 can generate a stable color subcarrier frequency Fsc with crystal precision. In this way, the color subcarrier is regenerated by an all-digital phase-locked loop, and stable color demodulation can be performed.

In addition, the color subcarrier frequency can be changed freely by changing the setting value of the color subcarrier frequency, which is the NT'SC method.

NTS'C all over the world such as PAL system and NPAL system.

It is possible to correspond to the color subcarrier frequency of the PAL system by simply changing the setting data.

Next, the remodulation circuit will be explained with reference to FIG. In order to restore the sampling frequency number of the output color difference signal 8.9 of the comb filter 105 to the original value, interpolation is performed by the low-pass filter 201. Furthermore, the outputs of SIN and CO8ROM 116 are applied to the delay circuit 204, and multiplications 1109, 110, . Orthogonal modulation is performed by correcting delay times caused by the low-pass filter 104, comb filter 105, low-pass filter 201, and sub-samples, multiplication by multipliers 205 and 206, and addition by adder 207.

Thereafter, an inverse gain correction circuit 203 corrects the shift amount by the shifter 102 and the gains by the bandpass filter 101, low-pass filter 104, etc., and generates a carrier color signal of the composite video signal 3. The delay time of this carrier color signal 4 is corrected by a delay circuit 301, and the carrier color signal is canceled by subtracting by a subtracter 302, so that the luminance signal Y'
You can get 5. In the case of the NTSC system, the carrier chrominance signal 4 re-modulated by the comb filter 105 is interleaved with the luminance signal, so the output luminance signal 5 has wideband characteristics, and as a whole becomes a comb filter for the luminance signal. There is.

In the case of a non-standard NTSC signal such as a VTR, the comb filter 105 cannot completely remove the luminance signal, so even if re-modulated, there is no interleaving relationship, and even the luminance signal component is subtracted, resulting in a trap-like signal. Becomes a characteristic. In this way, the carrier color signal can be removed from the composite video signal regardless of whether it is regular or non-regular.

In addition, in the case of the PAL system, LH memory does not have a perfect comb-shaped characteristic, so it has a trap-like characteristic.
Removal of the carrier color signal is possible. In that case, the (2) signal side of the comb filter 105 needs to be subtracted. If a color signal comb filter using 2H memory can be used, a luminance signal comb filter similar to that used in the NTSC system can be used. In the case of the NTSC method, further improvement in toughness can be expected. In that case, the delay circuit 30
1 needs to be an IH delay circuit.

FIG. 4 is a block diagram showing another embodiment of the remodulation circuit 200. The color signal processing circuit 100 is the same as that shown in FIG. 3, so a description thereof will be omitted. In the remodulation circuit of FIG. 4, instead of delaying the orthogonal color subcarriers, the oscillation phase of the digital oscillation circuit 115 is changed by the adder 20 by an amount corresponding to the delay time.
A method was adopted in which correction data 56 was given to 9. Although the SIN and CO3 ROM 208 are required instead, the amount of hardware can be made smaller than that of the delay circuit 204 in some cases. Furthermore, by changing the value of the correction amount 56, it is possible to support both the NTSC system and the PAL system. Also, if this method is used, SIN and C'O'S R'OM'2
A part of gain correction such as a band pass filter 5° 24 101 can be included in '0.8, and the inverse gain correction circuit can be simplified.

In the above description, the subtracter 302 is used, but if the polarity of the carrier color signal is reversed at the time of calculation by means such as reversing the polarity within the remodulation circuit or before it, the adder 302
Of course, you may also use .

Effects of the Invention As described above, the present invention processes color signals using a clock synchronized with a frequency that is an integral multiple of a horizontal synchronization signal.

It realizes luminance signal processing and synchronization signal processing, and in particular, it separates the luminance signal by quadrature modulating the demodulated color difference signal again and subtracting it from the composite video signal, and converts it into a normal signal or a non-normal signal. It is possible to separate the bright signal without switching the circuit regardless of the circuit, especially when using regular NT.
In the case of an SC signal, it becomes a comb-shaped filter for the luminance signal, and an excellent effect can be obtained in that a broadband luminance signal can be obtained.

Furthermore, the present invention can process color television signals having orthogonally modulated carrier color signals from all over the world at the same clock frequency, provide sampled data on a grid to the image memory, and share the image memory. It also has the effect of being able to be converted into

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention;
FIG. 2 is a block diagram showing the configuration of a synchronization signal processing circuit, FIG. 3 is a block diagram showing the configuration of a color signal processing circuit and a remodulation circuit, and FIG. 4 is a block diagram showing another embodiment of the remodulation circuit. A block diagram of a signal processing circuit and a remodulation circuit. FIG. 5 is a block diagram showing the configuration of a conventional example. 1...Input composite video signal, 2...A/
D converter, 3... Digitized composite video signal, 40... Clock generation circuit, 100...
. . . Color signal processing circuit, 200 . . . Remodulation circuit, 401 . . . Horizontal phase synchronization circuit.

Claims (6)

[Claims] (1) An analog/digital converter that samples and quantizes an input composite video signal having an orthogonally modulated carrier color signal, and converts the quantized composite video signal into an integer multiple of the horizontal synchronizing signal using a horizontal digital phase-locked loop. a synchronous signal processing circuit that generates at least one clock reference signal that is synchronized with a frequency; a clock generation circuit that generates at least one clock that is synchronized with the clock reference signal;
A color signal processing circuit that reproduces a color subcarrier from a quantized composite video signal using a digital phase-locked loop and performs color demodulation using synchronous detection, and a color signal processing circuit that regenerates the demodulated color difference signal by orthogonally modulating it using the reproduced color subcarrier and then transports it. It is equipped with a remodulation circuit that reproduces the color signal, a delay circuit that corrects the delay of the carrier color signal, and a difference calculation circuit, and separates the luminance signal by subtracting the remodulated carrier color signal from the composite video signal. A digital television receiver featuring: (2) The synchronization signal processing circuit includes a low-pass filter that suppresses the high-frequency components of the quantized composite video signal, a synchronization separation circuit that separates the synchronization signal from its output, and a synchronization separation circuit that divides the clock frequency and outputs horizontal pulses. A frequency divider circuit, a phase comparison circuit that compares the phase of the horizontal synchronization signal and the horizontal pulse, a loop filter that determines the loop response, an adder circuit that adds the clock reference frequency value to the error value, and the oscillation frequency is controlled by the input value. a crystal oscillation circuit that supplies a stable crystal clock to the digital oscillation circuit;
A digital/analog conversion circuit converts the output of the digital oscillation circuit into an analog clock reference signal, and the output of the clock generation circuit that generates at least one clock synchronized with the clock reference signal is sampled and used as an operating clock. The digital television receiver according to claim 1, wherein a horizontal phase-locked loop is constructed by doing this. (3) The color signal processing circuit includes a bandpass filter that extracts the carrier color signal component from the quantized composite video signal, and a coarse gain that first detects and makes constant the amplitude of the demodulated burst and color signal. ACC including shifter for adjustment
Circuit 1, a color demodulation circuit that performs synchronous detection using a digitally reproduced color subcarrier and a multiplier, and a color demodulation circuit that suppresses high frequency components of the synchronously detected demodulated color signal and lowers the sampling frequency. The ACC circuit 2 includes a low-pass filter, a comb filter that suppresses residual luminance signal components from its output, and a multiplier that performs finer gain adjustment. Claim No. 1, characterized in that an output color difference signal is output, and reverse gain adjustment in a remodulation circuit is facilitated.
1) The digital television receiver described in item 1). (4) The color demodulation circuit includes a burst gate that detects a burst signal from the demodulated color difference signal, a loop filter that determines a loop response, an addition circuit that adds a color subcarrier frequency value to the output error signal, and an addition circuit that adds a color subcarrier frequency value to the output error signal. A division circuit that divides the output of the circuit by the clock reference frequency setting value that includes the error of the horizontal phase-locked loop to cancel the effects of clock frequency fluctuations, and a digital oscillation circuit that digitally generates color subcarriers based on the input value. , a SIN and COSROM that converts the output into orthogonal color subcarriers, and a multiplier that performs synchronous detection with the input carrier color signal and the orthogonal color subcarrier, and these constitute a digital phase-locked loop. 3. A digital television receiver according to claim 1, wherein the digital television receiver reproduces stable color subcarriers and performs color demodulation. (5) The remodulation circuit includes a low-pass filter for interpolation that restores the color difference signal whose sampling frequency has been lowered, and a color subcarrier whose delay time from the color demodulation circuit to the output of the low-pass filter is orthogonal to each other. The demodulated color difference signal is equipped with a delay circuit for correction, a multiplier and an adder for performing orthogonal modulation, and an inverse gain correction circuit for correcting the gain in the color signal processing circuit to the amplitude at the time of input to the bandpass filter. A digital television receiver according to claim 1, wherein the digital television receiver modulates the signal into a carrier color signal again. (6) The re-modulation circuit includes an interpolation low-pass filter that restores the color difference signal whose sampling frequency has been lowered to its original value, and corrects the delay time from the color demodulation circuit to the output of the low-pass filter with respect to the color subcarrier. The adder is equipped with an adder that performs phase correction of the color subcarrier, and a sine and cosine ROM that converts the output into orthogonal color subcarriers, and modulates the demodulated color difference signal back into the carrier color signal. A digital television receiver according to claim (1).