JP2563418B2 - Digital television receiver - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital television receiver that performs digital signal processing such as demodulation of an NTSC system or PAL system video signal, and particularly a system for the NTSC system. It relates to a lock reproducing method.

2. Description of the Related Art In recent years, due to the rapid progress of semiconductor technology, the speed and capacity of semiconductor integrated circuits have increased, and LSIs that use digital signal processing for real-time signal processing of video signals.
Memory is often used. In the case of NTSC signal processing, color demodulation and Y / C separation are easy, so processing is often performed with a clock synchronized with a frequency four times as high as the burst signal. However, in the case of a non-standard signal such as a VTR signal, or when storing an image in a frame memory and performing two-dimensional image processing such as scan conversion, the line-lock method in which sample points are arranged in a grid pattern is used. It is better to use a clock.

JP-A-52-86722 and JP-A-61-161902 disclose examples of digital television receivers using a line lock type clock.

Hereinafter, an example of a conventional digital television receiver will be described with reference to the drawings.

FIG. 2 is a block diagram showing the main components of a conventional digital television receiver. In FIG. 2, 1
Is an analog-to-digital (A / D) conversion circuit. Reference numeral 2 is a bandpass filter, and 3 is an automatic color gain control (ACC) circuit, which controls the burst amplitude to be constant. 4 is a color demodulation circuit by synchronous detection using a multiplier, 5 is a low-pass filter, 6 is a comb filter, 7 is a burst gate, and 8 is a burst gate.
Is a loop filter, 9 is an adder for adding the loop error and the setting value of the color subcarrier frequency, 10 is a divider circuit for canceling the influence of the clock fluctuation, and 11 is a color subcarrier according to the given setting value. It is a digital oscillator circuit and constitutes a digital phase-locked loop (PLL). The above is the configuration of the color signal processing circuit.

Further, 12 is a low-pass filter, 13 is a sync separation circuit, 14 is a phase comparison circuit, 15 is a loop filter, 16 is an adder circuit for setting the clock frequency, 17 is a digital oscillator circuit, 18 is a stable clock for the digital oscillator circuit 17. A crystal oscillator circuit to be supplied, 19 is a digital / analog (D / A) conversion circuit, and 20 is an analog multiplication circuit, which generates a clock by multiplying the triangular wave output from the D / A conversion circuit 19 by 2 and outputs it to all circuits. Supply the clock. Reference numeral 21 is a frequency dividing circuit. The above constitutes the horizontal PLL.

The operation of the digital television receiver configured as described above will be described below.

First, the high-pass noise of the video signal digitized by the A / D conversion circuit 1 is suppressed by the low-pass filter 12,
The sync separation circuit 13 compares the black level to separate the composite sync signal component. This signal is phase-compared with a horizontal pulse obtained by dividing the clock by N by a frequency dividing circuit 21, and the error signal component thereof is smoothed by a loop filter 15 every horizontal period (H). The smoothed error signal is added to the set value Nf _H / (2F _x ) in the clock frequency setting addition circuit 16. Here, N is the frequency division ratio of the frequency dividing circuit 21, F _H is the horizontal frequency, F _x is the crystal oscillation frequency, and this F _x is a frequency higher than NF _H. The added value is given to the digital oscillator circuit 17,
Outputs sawtooth wave data with a frequency of NF _H / 2. This data is shaped into a triangular wave and the D / A conversion circuit 19 converts it into an analog triangular wave with the frequency of NF _H.
The clock with the _H frequency is regenerated. Analog multiplier circuit 2
0 can be realized by using an analog PLL circuit, for example.

Problems to be Solved by the Invention However, in the configuration in which the clock is formed by the horizontal PLL as described above, the control range of the clock is as wide as ± 7% and high in order to cope with the non-standard signal input from the VTR or the like. It becomes a PLL with a frequency division ratio, and there are problems such as deterioration of clock stability and occurrence of jitter. Also, in the case of standard TV signals, the clock control range is only about ± 0.015% and the phase comparison degree is inferior to the burst lock with a high degree of phase comparison. As a result, there is a problem that the Y / C separation characteristics may deteriorate when a frame comb filter is constructed.

In view of the above problems, the present invention reproduces a clock by a horizontal PLL as usual for a non-standard signal such as a VTR,
It is intended to provide a digital television receiver capable of reproducing a clock by a color width carrier wave PLL for a standard TV signal.

Means for Solving the Problems In order to solve the above problems, the digital television receiver of the present invention takes advantage of the fact that both the horizontal phase synchronizing circuit and the color subcarrier phase synchronizing circuit are configured by digital circuits. It is equipped with a selection circuit that selectively outputs the loop filter output of the horizontal phase synchronization circuit and the loop filter output of the color subcarrier phase synchronization circuit. When the horizontal phase synchronization circuit is unlocked and a non-standard signal is input, the horizontal phase synchronization circuit Of the color subcarrier phase synchronization circuit when the standard signal is input.

Operation With the above configuration, the loop filter output of the horizontal phase synchronization circuit is selected when the horizontal phase synchronization circuit is unlocked and when the non-standard signal is input, and the clock is regenerated in the line lock mode. This means that the loop filter output is selected and clock recovery is performed in burst lock mode. As a result, the number of signal samples becomes constant for each line by following a non-standard signal such as a VTR, which facilitates memory application. Further, the burst lock mode is applied to the standard signal, and a highly accurate clock with less jitter can be generated.

Embodiment A digital television receiver according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the main configuration of a digital television receiver according to an embodiment of the present invention. Second
The same reference numerals are given to the same configurations as the drawings. In FIG. 1, 1a and 1b are analog / digital (A / D) conversion circuits. Reference numeral 2 is a bandpass filter, and 3 is an automatic color gain control (ACC) circuit, which controls the burst amplitude to be constant. 4 is a color demodulation circuit by synchronous detection using a multiplier,
5 is a low-pass filter, 6 is a comb filter, 7 is a burst gate, 8 is a loop filter, 9 is an adder that adds the loop error and the setting value of the color subcarrier frequency, and 10 is a division for canceling the influence of clock fluctuation. A circuit, 11 is a digital generation circuit for generating a color subcarrier according to a given set value, and constitutes a digital phase synchronization circuit (PLL). The above is the configuration of the color signal processing circuit.

Further, 12 is a low-pass filter, 13 is a sync separation circuit, 14 is a phase comparison circuit, 15 is a loop filter, 22 is a selection circuit for selecting loop filter output, 22 is standard / non-standard (TV / VT
R) detection circuit, 16 adder circuit that sets the clock frequency, 17 digital oscillation circuit, 18 crystal oscillation circuit that supplies a stable clock to the digital oscillation circuit, 19 digital-analog (D / A) conversion circuit, Reference numeral 20 denotes an analog multiplication circuit which doubles the triangular wave output from the D / A conversion circuit 19 to generate a clock and supplies it to all circuits. Reference numeral 21 is a frequency dividing circuit. The horizontal phase locked loop (PLL) is configured as described above.

The operation of the digital television receiver of this embodiment constructed as above will be described below.

First, the video signal digitized by the A / D conversion circuit 1b has high-pass noise suppressed by the low-pass filter 12,
The sync separation circuit 13 compares the black level to separate the composite sync signal component. This signal is phase-compared with a horizontal pulse obtained by dividing the clock by N by a frequency dividing circuit 21, and the error signal component thereof is smoothed by a loop filter 15 every horizontal period (H).

In the VTR mode, the error signal smoothed by the selection circuit 23 is directly added to the set value Nf _H / (2F _x ) in the clock frequency setting addition circuit 16. Here, N is the division ratio of the frequency dividing circuit 21, F _H is the horizontal frequency, F _x is the crystal oscillation frequency,
This F _x has a higher frequency than NF _H.

Loop filter 8 of color subcarrier PLL in TV mode
The output of is selected by the selection circuit 23 and added to the addition circuit 16. The added value in the adding circuit 16 is given to the digital oscillating circuit 17 and outputs sawtooth wave data having a frequency of NF _H / 2. This data is shaped into a triangular wave D /
The A conversion circuit 19 produces an analog triangular wave of NF _H frequency, and the analog multiplication circuit 20 reproduces the clock of NF _H frequency. The analog multiplication circuit 20 is, for example, an analog PL.
It can be realized by using the L circuit.

As described above, according to this embodiment, the selection circuit 23 is connected to the TV / VTR.
Depending on the mode, the loop filter output from the color subcarrier PLL and the loop filter output from the horizontal PLL are switched and output, so that the burst lock mode is set in the case of a standard TV signal and a stable clock with little jitter is reproduced. can do.

In addition, taking advantage of the fact that both the horizontal PLL and the color subcarrier PLL are composed of digital circuits, the standard / non-standard (TV / VTR) mode is determined by measuring the error and fluctuation components of each loop filter output. By connecting the output of the TV / VTR detection circuit 22 to the control input of the selection circuit 23, the clock can be automatically switched.

Although the clock frequency and the like are not specified in the above embodiment, they are extremely flexible and can be freely determined. As an example, the clock frequency is 1
3.5MHz, division ratio N = 858, crystal oscillation frequency is 24.576MHz, as another example, clock frequency is 14.31818MHz,
The frequency division ratio N = 910 and the crystal oscillation frequency is 28.63636 MHz.

EFFECTS OF THE INVENTION According to the present invention, the fact that both the horizontal phase synchronization circuit and the color subcarrier phase synchronization circuit are composed of digital circuits makes the most of the loop filter output of the horizontal phase synchronization circuit and the color subcarrier phase synchronization circuit. By providing a selection circuit that selectively outputs the loop filter output, the loop filter output of the horizontal phase synchronization circuit is selected when the horizontal phase synchronization circuit is unlocked and a non-standard signal is input, and the clock is regenerated in the line lock mode. When the signal is input, the loop filter output of the color subcarrier phase locked loop is selected and the clock is regenerated in the burst lock mode. The flexibility of the line clock mode, the ease of memory application, and the stability of the clock in the burst lock mode are provided. It is possible to achieve both low jitter characteristics and low jitter characteristics.

[Brief description of drawings]

FIG. 1 is a block diagram showing the main structure of a digital television receiver according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the main structure of a conventional digital television receiver. 1 ... A / D conversion circuit, 4 ... color demodulation circuit, 7 ... burst gate, 8 ... loop filter, 10 ... division circuit, 11
...... Digital oscillator circuit, 13 …… Synchronous separation circuit, 14 ……
Phase comparator circuit, 15 ... Loop filter, 17 ... Digital oscillator circuit, 20 ... Analog multiplication circuit, 22 ... Standard / non-standard detection circuit, 23 ... Selection circuit.

Claims (3)

(57) [Claims] 1. An analog / digital converter for sampling and quantizing an input video signal, and a horizontal synchronizing signal from the quantized video signal by a horizontal phase synchronizing circuit including at least a first loop filter and a digital oscillating circuit. Of a clock sub-carrier that regenerates at least one clock synchronized with a frequency that is an integral multiple of the frequency, and a color sub-carrier phase synchronization circuit that includes at least a second loop filter that operates at the clock, and regenerates the color sub-carrier by performing synchronous detection. A color signal processing device for performing demodulation, and a first of the horizontal phase synchronization circuit.
A loop filter output and a selection circuit for selectively outputting the second loop filter output of the color subcarrier phase lock circuit between the loop filter and the digital oscillator circuit, and when the horizontal phase lock circuit is not locked and is not standard. When the signal is input, the first loop filter output of the horizontal phase lock circuit is selected and the clock is regenerated in the line lock mode. When the standard signal is input, the second loop filter output of the color subcarrier phase lock circuit is selected and the burst lock mode is selected. A digital television receiver characterized by clock reproduction. 2. A low pass filter for suppressing high frequency noise of a quantized video signal, a sync separation circuit for separating a sync signal, a divider circuit for dividing a clock and outputting a horizontal pulse, and a horizontal sync signal. And a phase comparison circuit that compares the horizontal pulse in phase, a first loop filter, a selection circuit that selectively outputs the outputs of the first and second loop filters, and a first addition circuit that sets the clock frequency. A digital oscillating circuit whose oscillation frequency is controlled by a value, a crystal oscillating circuit for supplying a stable clock to the digital oscillating circuit, a digital / analog converting circuit for digital / analog converting the output of the digital oscillating circuit, and this digital And an analog multiplication circuit for multiplying the output of the analog conversion circuit, and the output of the analog multiplication circuit is a line lock mode. A clock reproduction device that constitutes a horizontal phase synchronization circuit as a clock, a bandpass filter that extracts a color signal component from a quantized video signal, a color subcarrier that is digitally reproduced, and color demodulation by synchronous detection by a multiplier. A color demodulation circuit that performs the above, a low-pass filter that suppresses the high frequency component of the demodulated color signal, a burst gate that extracts the burst signal from the demodulated color difference signal, a second loop filter, and a color subcarrier frequency are set. A second adder circuit, a divider circuit that divides the output of the second adder circuit by the frequency control data of the horizontal phase synchronization circuit, and a digital oscillator circuit that digitally generates a color subcarrier according to a set value. 2. A digital signal processing apparatus according to claim 1, further comprising a color signal processing device for performing color demodulation by a color sub carrier phase synchronization circuit provided. Television receiver. 3. A standard / non-standard detector for detecting a standard signal or a non-standard signal from the output of each loop filter of the color sub-carrier phase synchronization circuit and the horizontal phase synchronization circuit and automatically switching the selection circuit. A digital television receiver as set forth in claim 1.