KR0171821B1 - Nervous clock signal generator for video recorder - Google Patents

Abstract

A video recorder for recording a composite video signal has an analog to digital converter for digitizing a sample of the composite video signal to be recorded. The sync separator separates the horizontal sync information from the composite video signal to be recorded. The chromaticity signal information region of the composite video signal to be recorded by the filtering is separated, and the downlink frequency converter generates the color undersignal by mixing the separated chromaticity signal information with the non-carrier signal. A control oscillator is provided for generating a continuous pixel clock signal at a predetermined ratio whose frequency and phase are determined based on the oscillator control signal. The ratio is at least twice the frequency of the non-carrier signal and is sampled by an analog-to-digital converter. The ratio is set. The counter includes a means for counting the number of pixel clock signals provided by the control oscillator, counting the number of pixels generated at four scan lines, and then returning the count to an initial value. The frequency divider divides the coefficients by the prescribed factors to generate a divisor of the coefficients. To further develop the error signal, the discriminator determines when the divisor of the coefficients from the counter differs from the frequency or phase from the horizontal sync information separated from the composite video signal to be recorded. The low pass filter responds to the error signal to generate an oscillator control signal. The phase-locked loop connection portion comprising the control oscillator, the counter, the inter-frequency divider, the discriminator and the low pass filter is thus completed and the non-carrier signal is derived in response to the condition of the counter. This derivation is achieved by using a sinusoidal lookup table stored in a read only memory, by heterodyning a stable oscillator and a high frequency vibration, or by using a divisor of this vibration obtained by frequency division.

Description

Video Recorder's Nuverse Clock Signal Generator

1 is a schematic diagram of a video recording circuit embodying the present invention.

2 is a schematic diagram modified to improve the video recording circuit operation of FIG. 1 in accordance with further embodying the present invention.

3 is a schematic of a non-standard input detector used in the video recording circuits of FIGS. 1 and 2, which determines how many of the video signals provided for recording are a timebase error that undergoes proper construction filtering as a step in the recording process. diagram.

4 and 5 are schematic diagrams of alternative arrangements for generating a 4.21 MHz clock clock in the video recording circuit of FIG. 1 according to the invention, respectively.

FIG. 6 is a schematic diagram of a playback circuit for use with the FIG. 1 video recording circuit modified by FIG.

7, 8, and 9 are schematic diagrams of an apparatus for generating a stable clock of 4.21 MHz in the regeneration circuit of FIG. 6, respectively.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video recording and reproducing system, and more particularly, to down-convert a chromaticity signal separated from a composite video signal to a color under signal, and to include a chromaticity signal in a reproduced composite video signal during reproduction. It relates to the generation of a negative clock signal used to up-convert a color under signal to a chroma signal.

Recently, with the development of digital processing technology for video signals, home VCRs that provide high resolution and high quality images have emerged. Filed on August 17, 1990 in the name of the invention, a video signal recording system improved by the inventors and their colleagues, US Patent Application No. 07/569 029 (Korean Patent Application No. 1991-3187 The specification and drawings (the invention has been transferred to Samsung Electronics Co., Ltd. and paid the patent issuance fee) are hereby incorporated by reference. The system was developed to provide a home VCR with a resolution that is compatible with standard VHS systems.

The video signal recording system described above in US patent application Ser. No. 07/569 029 digitizes the composite video signal and applies the composite video signal to a suitable digital time-space filter to separate the digitized luminance signal substantially free of chromaticity signal information. Let it work. The digitized luminance signal is supplied to an input signal of a digital band separation filter, and the digital band separation filter generates a digital low pass filter response and a digital high pass filter response to the digitized luminance signal. Responds to the appearance of crossover in the middle frequency band. The digital filter highpass response is properly de-emphasis with respect to the digital lowpass filter response and then folded around the middle frequency band to cover the same region in the baseband as the standard spectrum of the digital lowpass filter response. It appears as an inverted spectrum occupying. A reduced bandwidth luminance signal accompanied by horizontal and vertical synchronization signals is used to modulate the frequency of the luminance signal carrier and to generate a luminance signal region of the signal recorded on the videotape in substantially the same way as a standard VHS system. .

The reproducing circuit of the video signal recording and reproducing system described above in US patent application Ser. No. 07/569 029 is a time-base error in the reduced-bandwidth luminance signal which is recovered in analog form from a videotape in a standard manner and continues to be digitized during reproduction. A time base corrector (TBC) capable of correcting (time base error: TBE) is provided. TBC is a device that removes time-base errors contained in video signals by a memory acting as a time-base buffer. According to the clock signal synchronized with the video signal having the TBE, the video signal having the TBE is written into the memory and read from the memory according to the stable clock signal. The term TBE refers to jitter entering a signal by mechanical elements in a VCR record and playback system, such as tape speed variation and tape tremor during recording and playback.

The luminance signal of the time-base corrected reduced bandwidth is not folded and this unfolded signal is subjected to appropriate digital construction filtering to separate the full spectrum, which is a digitized luminance signal that is substantially free of folding artifacts. The high frequency region of the separated and digitized luminance signal that is substantially free of folding artifacts is then re-emphasis.

The video signal recording system described in US patent application Ser. No. 07/569 029, in some respects, follows a standard VHS system process for recording and reproducing chromaticity signal information in a color under format. The standard VHS system process for reproducing the chromaticity signal information recorded in the color under format includes the measurements described in the next paragraph, which prevents the time-base error (TBE) in the video signal from introducing color errors. . For example, when a composite video signal to be recorded is supplied from another video recorder, a TBE occurs in the composite tape video signal to be recorded due to a tape shake or a change in speed of the tape transmission used for reproducing the signal. During recording, TBE also occurs due to changes in the speed of the tape transfer used in the recording or the shaking of the tape. Even during continuous playback, TBE also occurs due to a change in the speed of the tape transfer used in the playback, tape shaking, or the like.

In recording, the sideband of the separated chroma signal with a 3.58 MHz suppressed broadcast wave is heterodyne with 4.21 MHz oscillation to generate a complex amplitude modulated sideband of the 629 kHz suppressed carrier. The color bursts that interfere during the downlink frequency conversion process to generate the color undersignal are heterodyned down to 629 kHz. The 4.21 MHz oscillation used in the downlink frequency conversion process is supplied from a phase-locked oscillator (PLO) and is called a so-called "nervous clock signal." The PLO is equipped with a voltage-controlled oscillator (VCO), where the frequency and phase of the VCO are electrically controlled by an error signal and synchronized in multiples of the scan line frequency. To achieve this synchronization, the VCO is included in the corrective-feedback loop connection, in which the VCO feeds the oscillated oscillation into the frequency divider, and the frequency divider is a weak vibration of the vibration. Is supplied to the frequency and phase comparator, and the frequency and phase comparator feeds the result of the comparison to the loop filter, the loop filter determines the speed and the speed and error signal can be reduced by the loop connection, and the vibration of the VCO To adjust its frequency and phase, the filter response is applied to the VCO, completing a correction feedback loop that controls the frequency and phase of the vibration from the VCO to reduce the error signal. If the filter response time constant is not longer than the scan line duration, the frequency and phase of 4.21 MHz will change according to the TBE in horizontal sync. In downlink frequency conversion to 629 kHz, the TBE in the chroma signal is differentially coupled to the 4.21 MHz oscillation so that the color undercarrier is completely free of the TBE. In order to generate color burst and chroma signal sidebands during reproduction during up-frequency conversion, the 4.21 MHz stable oscillation is heterodyne with the color undersignal and the 3.58 MHz carrier in the chroma signal sideband is completely free of TBE.

An interesting aspect of the present invention is that when digitizing a composite video signal, it is necessary to generate a clock signal that is used by the analog-to-digital converter to determine the sampling time of the composite video signal, wherein the clock signal times the resulting digital sample. Used to clock into axis compensation memory. As we have already seen, when the composite video signal is fed from another video recorder, TBE occurs in the composite video signal to be recorded due to the tape shake or the change in the speed of the tape transmission used for playback. While digitizing the composite video signal provided for recording, the clock signals for the analog-to-digital converter are tracked separately from the composite video signal to be digitized in order to track the TBE by varying the sampling instants of the pixels of the horizontal scan line with the analog-to-digital converter. It is supplied from a phase-locked oscillator (PLO) that is synchronized with the pulse. The PLO has a voltage controlled oscillator (VCO), the frequency and phase of the VCO being electrically controlled by an error signal and synchronized to a multiple of the scanline frequency. (The VCO can be used instead of a current controlled oscillator. In fact, anyone familiar with PLO design can see it well.)

To achieve this synchronization for multiples of the horizontal scan line, the VCO is included in a corrective-feedback loop connection, in which the VCO feeds the oscillated oscillation into the frequency divider and the frequency The divider supplies the subtractive vibration of the vibration to a frequency and phase comparator, the frequency and phase comparator feeds the comparison result to a loop filter which determines the speed and the speed and error signal can be reduced by the loop connection part. The filter response is applied to the VCO to adjust the frequency and phase of the oscillation of the VCO, thus completing a correction feedback loop that controls the frequency and phase of the oscillation from the VCO to reduce the error signal. If the filter response time constant is not longer than the scan line duration, the frequency and phase of the clock signal supplied from the VCO to the analog-to-digital converter varies with the TBE in horizontal sync. The TBE in horizontal sync is the TBE index in the luminance signal so the TBE in the luminance signal is compensated when the time base corrector memory is read according to a stable clock.

According to the present invention, a sinusoidal signal of 4.21 MHz, which is used in the down frequency conversion and up frequency conversion process in combination with a color under signal, does not occur directly from a phase locked analog oscillator oscillating at 4.21 MHz. Instead, the 4.21 MHz frequency of the negative clock signal is derived from the high frequency vibration and provided as a clock signal to the analog-to-digital converter used to digitize the luminance signal. This derivation is achieved by using a sinusoidal look-up table stored in read only memory (ROM), by heterodyneing a stable oscillator with high frequency vibration, or by using a weak frequency vibration of high frequency vibration obtained by frequency division. .

One embodiment of the invention resides in a video recorder for recording a composite video signal, which has an analog to digital converter for digitizing a sample of the composite video signal to be recorded. The sync separator separates the horizontal sync information from the composite video signal to be recorded. The chromaticity signal information region of the composite video signal to be recorded by the filtering is separated, and the downlink frequency converter generates the color undersignal by mixing the separated chromaticity signal information with the non-carrier signal. A control oscillator is provided for generating a continuous pixel clock signal at a predetermined ratio whose frequency and phase are determined based on the oscillator control signal. The ratio is at least twice the frequency of the non-carrier signal and is sampled by an analog-to-digital converter. The ratio is set. The counter includes a means for counting the number of pixel clock signals provided by the control oscillator, counting the number of pixels generated at four scan lines, and then returning the count to an initial value. The frequency divider divides the coefficients by the prescribed factors to generate a divisor of the coefficients. To further develop the error signal, the discriminator determines when the divisor of the coefficients from the counter differs from the frequency or phase from the horizontal sync information separated from the composite video signal to be recorded. The low pass filter responds to the error signal to generate an oscillator control signal. The phase-locked loop connection portion comprising the control oscillator, the counter, the frequency divider, the discriminator and the low pass filter is thereby completed and a non-carrier signal is derived in response to the condition of the counter. This derivation is achieved by using a sinusoidal lookup table stored in a read only memory, by heterodyning a stable oscillator and a high frequency vibration, or by using a divisor of this vibration obtained by frequency division.

Referring to FIG. 1, a recording circuit of a video recording and reproducing system embodying the present invention includes a chromaticity signal separator 10 connected to separate a chromaticity signal from a composite video signal, and a nuber sine carrier signal generator 11 at 4.21 MHz. A down-frequency converter 12 for generating a color under signal in response to the received chroma signal and a 4.21 MHz nubber sine carrier signal, a first analog-to-digital converter (ADC1) 13 for a composite video signal, and a second for color under signal. 2 analog-to-digital converter (ADC2) 14, a first first input / output (FIFO) memory 15 for digitized composite video signals, a second first input / output (FIFO) memory 16 for digitized color undersignals, A chroma signal recording processor 17, a digital adder 18 for combining the chroma signal with the same sideband, and to separate horizontal and vertical sync pulses from the composite video signal. And a sync separator 19. The first time axis corrector TBC1 is formed from 15 as a first entry / exit memory in combination with a write address generator 20 and a read address generator 30. The second time base corrector TBC2 is formed from the first entry / exit memory 16 combined with the write address generator 20 and the lead address generator 30. In addition, the recording circuit further includes a luminance signal recording processor 40 and according to the present invention, in order to modify the connection in the luminance signal recording processor 40 when a complex video signal having excessive TBC is received for recording in the luminance signal processor 40. A multiplexer 49 is provided.

The write address generator 20 is a first phase locked loop PLL1 having 21-25 elements. The low pass filter 21 sets the loop time constant τ ₁ for the error signal of PLL1 and the loop time constant τ ₁ is hardly longer than the duration of the horizontal scan line. The voltage controlled oscillator 22 oscillates at or near a frequency that is many times (eg 640) the horizontal scan line frequency controlled by the PLL1 error signal filtered by the low pass filter 21. Vibration from VCO 22 controls the time of sampling performed by analog to digital converters 13 and 14. The write address counter 23 is connected to count each period of the vibration coming from the oscillator 22. The coefficient 320 of the write address counter 23 is decoded by the decoder 24 as a first input signal to be supplied to the frequency and phase comparator 25. The second input signal supplied to the comparator 25 includes a separate sync pulse. Comparator 25 is one of a known type and generates an output signal that is proportional to the differential shift between corresponding edges of the first and second input signals. Comparator 25 feeds its output signal to low pass loop filter 21 and ends the phase locked loop PLL1. The loop filter 21 has a time constant that is almost no longer than the duration of one horizontal scan line, and the response of the phase locked loop PLL1 is to the separated horizontal sync pulse rather than the vertical sync pulse and is fast enough to follow the timebase error of the input signal very accurately. .

Lead address generator 30 is a second phase locked loop PLL2 having elements of 31-35. A low-pass filter 31 is set a loop time constant τ ₂ for a PLL2 error signal, the time constant τ ₂ is substantially 20 times the horizontal scanning line duration length. The voltage controlled oscillator 32 oscillates at or near a frequency that is many times (eg 640) the horizontal scan line frequency controlled by the PLL2 error signal filtered by the low pass filter 31. The lead address counter 33 is connected to count each period of the vibration coming from the oscillator 32. The coefficient 0 of the lead address counter 33 is decoded by the decoder 34 as a first input signal to be supplied to the frequency and phase comparator 35. The second input signal supplied to the comparator 35 includes a separate sync pulse. Comparator 35 has the same form as comparator 25, feeding its output signal to low-pass loop filter 31 and ending phase locked loop PLL2. The time constant of loop filter 31, which is almost 20 times the horizontal scan line duration, allows the second phase locked loop PLL2 to be synchronized with the vertical sync signal of the input signal but not to track fast changes in the input signal.

Therefore, the write address counter 23 quickly follows the time change of the composite video signal and simultaneously generates the write address signal WR, and the write address generator 20 digitizes the write address signal WR with the first FIFO memory for the digitized composite video signal. Supply to both of the second FIFO memories for color under signals. Since the lead address counter 33 is synchronized with the time of the composite video input signal averaged over a long period and is not affected by jitter on the tape, the lead address counter 33 is relatively suitable for the FIFO memory of the time base compensator TBC1 and the FIFO memory of the time base compensator TBC2. RD, which is a stable lead address signal, is generated.

It is assumed that FIFO memories 15 and 16 can each store a complete scan line of the pixel. The offset between the write address supplied to FIFO memories 15 and 16 and the lead address supplied to FIFO memories 15 and 16 is necessary for the memory to provide temporary storage without the risk of overwriting before reading. This offset is simply provided by arranging decoders 24 and 34 to generate semi-scanned outputs 1.

Elimination of the time axis error TBE1 in the high frequency component of the composite video signal by the time base corrector TBC1 is formed by the FIFO memory 15, and address generators 20 and 30 facilitate spatial processing of the luminance signal within the luminance signal recording processor 40. . The luminance signal recording processor 40 includes a suitable luminance signal separator having a time filter 41, a spatial filter 42, a copper signal detector 43, a soft switch 44, and a copper factor generator 45. The time filter 41 described above in US patent application Ser. No. 07/569 029 is a comb filter comprising a comb filter action of a form known as a frame comb, wherein the comb filter action is used for continuous television video. It is suitable for filtering out static areas rather than moving areas. In the patent application, the spatial filter 42 is a comb filter comprising a comb filter action of a form known as a line comb, which is suitable for filtering moving regions rather than still regions of continuous television images. The copper factor generator 45 generates copper factors K and K-1 recorded in the look-up table of the read-only memory (ROM) addressed by the detected copper signal values. Soft switch 44 determines the output ratio of temporal filter 41 and spatial filter 42 in response to the supplied copper factors K and K-1. This suitable luminance signal splitter, described more specifically in US patent application Ser. No. 07/569 029, follows a spectrum folder of the more suitable form described in US patent application Ser. No. 07/569 029. The signal processor 47 modulates the copper signal from the copper signal detector 43 into a four-phase carrier to generate a signal M composed of sidebands, which is interleaved with a color undersignal C. go to hole). Signals C and M are supplied to adder 18 as a mantissa input signal.

Only the modified region of the luminance signal recording processor 40 for carrying out the present invention will be described in more detail below. The difference between the configuration according to the invention and the configuration described in US patent application Ser. No. 07/569 029 is in response to a composite video signal classified by the nonstandard input detector 48 as a nonstandard input signal, which is generated by the detector 43. For motion signals ranging from arithmetic 0 for no motion to arithmetic 1 for full motion, multiplexer 49 selects arithmetic 1 for application to driver factor 45 and motion processor 47. This allows the output value K and 1-K from the driver factor generator 45, in the case of non-standard input signals, with or without the same signal, to be the condition of the luminance signal L to completely compose the spatially extracted luminance signal sample. That is, when a non-standard input signal is detected, the timebase corrected and digitized signal from FIFO memory 15 is first processed in the spatial domain to generate luminance signal L, which is provided as an output signal from luminance signal recording processor 40. do.

Non-standard input detector 48 generates a control signal, which is one of 1 and 0 depending on the input signal whether or not the input signal is a non-standard input signal comprising a TBE. Non-standard input detector 48 shown in FIG. It's a form of decision. Specific examples of such non-standard input detectors are described in more detail with reference to FIG. The nonstandard input detector 48 is not limited to this particular form, and all that is required for the configuration of the nonstandard input detector is that the nonstandard input detector only needs to detect whether the current input signal is a nonstandard signal including a TBE.

The remaining area of the recording device is not shown in FIG. 1 but is similar to that described in US patent application Ser. No. 07/569 029. The luminance signal L is converted from digital to analog form and used for frequency modulation of the FM carrier. The C + M output signal from adder 18 is converted from digital to analog form and added to the FM carrier. Helical scanning techniques are used to record the sum signal on a magnetic recording medium.

In the chroma signal recording circuit according to the present invention, the downlink frequency converter 12 receives the 4.21 MHz Foxx output signal of the 4.21 MHz Foxx signal generator 11 and a TBE appears in the resulting color under signal during the downlink frequency conversion of such chromaticity signal. The TEB introduced in the resulting color under signal corresponds to the TBE in the sampling clock supplied from the analog to digital converter 14. If digital samples are re-timed along a stable clock to generate regularly, the digital samples supplied from analog-to-digital converter 14 will be free of TBE with respect to the color undercarrier signal. Thus, uplink frequency conversion with a stable clock during playback may regenerate a chromaticity signal with no detectable error in the color subcarrier phase. This is similar to the prior art, except that the 4.21 MHz Foxx carrier was generated in another way. In the prior art, there is no time base correction of the luminance signal during recording, since it can generate a differential TBE between the luminance signal and the chroma signal which may cause a tracking problem of the luminance / chromatic signal during reproduction. Since the luminance signal is not digitized but goes through a digitized filter during recording, time axis correction of the luminance signal is not necessary. The process of reproduction in the prior art only up-converts the color undersignal by mixing the color undersignal with a stable 4.21 MHz sine wave supplied from the crystal oscillator, thereby doing chromaticity signal sidewaves for the composite video signal provided to the VHF television channel modulator. The band reoccurred. The carriers of the 4.21 MHz sine wave and the color undersignal both have no TBE, thus facilitating the synchronization of local color oscillators in the color television receiver. The pull-in range of the AFPC loop of the local color oscillator is much smaller than could ever be exceeded.

In videotape recorders, the luminance signal undergoes digitization and digitization filtering at the time of recording, and in particular, the time-base correction of the luminance signal is necessary to allow digital filtering to proceed when the digital filtering is in the transverse direction in the form of the recorder of the present invention. Do. The generation of the color undersignal obtained by the downlink frequency conversion of the 3.58 MHz chromaticity signal using the 4.21 MHz wide carrier is performed to correct the TBE for the color undercarrier frequency. However, the TBE for the functional modulation of the color undersignal is not performed with this process. Because the luminance signal is time-base corrected and the modulation function of the color under signal is not corrected, there is a differential time base error between the luminance signal information in the L signal and the chromaticity signal information in the digitized color under signal supplied by the analog-to-digital converter. . This differential timebase error is an obstacle to the chromaticity signal and luminance signal tracks on the screen during playback of the recorded video.

Obstacles to tracking of chromatic and luminance signals are eliminated by applying time base correction to the digitized color under signal supplied by ADC 14, which is applied to the digitized color under signal provided by ADC 13. Corresponds to The time base correction of the digitized color under signal is performed by the FIFO memory 16, which receives the lead address of the FIFO memory 15 as the write address and the write address of the FIFO memory 15 as the lead address. The adverse effects that the time base corrector TBC2 with elements 16, 20 and 30 have on the synchronization of the local color oscillator in the color television receiver in which the recorded video tape is played back will be compensated in the playback apparatus, which is described in FIG. It will be described in more detail when describing.

The chroma signal of the time base corrected and digitized color under signal is supplied from the FIFO memory 16 to the chroma signal recording processor 17. The chroma signal recording processor 17 limits the video response to the input chroma signal, and prevents anti-crosstalk into the fukiniki holes that the copper signal M supplied from the signal processor 47 will occupy. crosstalk) filtering.

FIG. 2 shows a modified luminance signal recording processor 400 which can be used in place of the recording luminance signal processor 40 in the recording circuit shown in FIG. 1, which is connected to elements 41-49 of the recording luminance signal processor 40. FIG. In addition, elements 401-404 are further provided. The luminance signal recording processor 400 responds to an input signal provided for recording classified as nonstandard to set the luminance signal signal M supplied to the adder 18 to zero. This process is more preferable than setting the copper signal M supplied to the adder 18 to a complete value in response to the non-standard classified input signal as performed in the recording circuit of FIG. This process is more desirable because it indicates undesirable crosstalk into the color undersignal C when the dynamic signal M is at full value. However, this process requires that some alternative method is provided for the signal operation of the videotape playback circuit, and the recorded video signal is recorded in the two-dimensional space domain and the field-to-field field in the time domain. It is not performed on -to-field or frame-to-frame conditions.

If the non-standard input signal detector 48 classifies the received input signal for recording as a standard or is substantially free of TBE, then it may selectively supply a logic 0 to the multiplexer 401 when the signal M from the signal processor 47 is selectively applied to the adder 18. When multiplexer 401 is used. When the non-standard input detector 48 classifies the received video input signal as non-standard or supplies logic 1 to the multiplexer 401, the multiplexer 401 selectively applies arithmetic 0 to the adder 18 rather than the copper signal M from the copper signal processor 47.

The ID signal generator 402 is in the form of generating an ID code that can identify the input signal as a non-standard signal in response to output 1 from the non-standard input detector 48. For example, the ID code may be a continuation of a pseudo noise sequence when a nonstandard input video signal is recorded, or a black level or a continuation of another pseudo noise sequence when a standard input signal is recorded. The multiplexer 403 receives the output signal of the spectrum folder 46 and the output signal of the ID signal generator 402 as input signals, and selects one of the input signals supplied from the gate signal generator 404 to the multiplexer 403 as the model on which the output signal of the multiplexer 403 is based. In response to a condition of a control signal supplied from the gate signal generator 404 to the multiplexer 403. The gate signal generator 404 responds to the vertical sync signal to generate a gate signal, which is outputted by the output signal of the multiplexer 403 in the active region of the predefined scan line during the vertical erase period or immediately following the vertical erase period. It is applied to the multiplexer 403 as a control signal which causes the condition of the multiplexer 403 to select the ID code input signal as the underlying model. The multiplexer 403 applies the time multiplexed chroma signal and the ID signal L + ID to the rest of the recording circuit in a conventional manner.

3 shows in more detail 48 possible configurations of a non-standard input signal detector. Digital adder 481 adds binary 320 (half of 640 pixels in the scan line) to the lead address from counter 33 to generate a TBE-free signal, which must be the same as the write address supplied from counter 23 and digital. Subtractor 482 is used to differentially couple the write address supplied from counter 23. The subtractor 482 feeds the differential signal to a digital average filter 483 that averages many samples. The absolute value circuit 484 rectifies the average in the output signal of the 482 supplied to the input signal. The output signal of the absolute value circuit 484 is fed to a threshold detector 485, which typically consists of a digital comparator. The threshold detector 485 generates logic 1 when the output signal of the absolute value circuit 484 exceeds a predefined value, which indicates that the received video input signal for recording is classified as nonstandard. If the output of the absolute value circuit 484 does not exceed the predefined value, the threshold detector 485 generates an output of logic 0, which indicates that the received video input signal for recording is classified as standard.

4 shows one method for generating a clock of 4.21 MHz in width without having another phase locked loop in addition to the phase locked loop PLL1 in write address generator 20. FIG. The write address counter 23 carries the carry in (CI) of the four-stage binary counter 231 from the VCO 22 to generate a 629 KHz square wave at the carry out (CO) connection of the four-stage binary counter 231. 429 binary counter 231, which counts the vibration of 10.1 MHz supplied to the connecting section, and 629 KHz square supplied to the carry-in connection of the 6-speed binary counter 232 from the carry-out connection of the 4-stage binary counter 231. A six-stage binary counter 231 that counts waves, and a decoder 233 that responds to the combined coefficients of counter 231 and counter 232 to reset the combined coefficient to 00 0000 0000 after the combined coefficient reaches 10 0111 1111. It is shown in more detail.

The Foxx clock generator 11 has an amplifier 111 that receives as input a 629 KHz square wave from the carryout (CO) connection of the counter 231, a crystal oscillator 112 that generates a very stable 3.58 MHz sine wave in time, and a horizontal scan line. A counter 113 for counting modulo-four, a programmable phase shifter 114 for shifting the 3.58 MHz sine wave by 90 ° according to the modulo fourth coefficient, and a phase shifted 3.58 MHz from phase shifter 114 It is shown in more detail that it has an uplink frequency converter 115 that generates a 4.21 MHz clock frequency in response to the sum frequency of the sine wave oscillation and the amplified 629 KHz output signal of the amplifier 111, where the 4.21 MHz signal is a phase locked loop PLL1. Since this time constant τ ₁ is short, it is negative.

In video recording, a programmable ideal phase 114 is used because there is an incremental shift of 90 ° from 4.21 MHz to the next scan line. This provides the desired 90 ° incremental shift for the 629 kHz color undercarrier from one horizontal scan line to the next horizontal scan line during video recording. As an example, the programmable idealizer 114 is an analog delay line that is tapped to supply 0 °, 90 °, 180 °, and 270 ° phases of a 3.58 MHz sine wave, and according to the modulo 4 coefficients of each scan line, The output has a multiplexer to select one of the four phases of the 3.58 MHz sine wave.

5 shows another method for generating a clock of 4.21 MHz in width without having another phase locked loop in addition to the phase locked loop PLL1 in write address generator 20. FIG. The Foxx 4.21 MHz clock can be generated using a dedicated memory 117 that stores sine and cosine wave lookup tables, and an appropriate one of these lookup tables is selected to lead according to the modulo 4 coefficients of the horizontal scan line. During video recording, there is a deviation of 90 ° at 4.21 MHz from one horizontal scan line to the next, so the lookup from the sine wave and the table is to be performed under four scan line period conditions. The digital-to-analog converter 118 converts the lead signal from the ROM 117 into an analog form for application to the downlink frequency converter 12 of FIG. 1 and FIG.

Those of ordinary skill in the art of ROM lookup table technology will benefit from the symmetry of the two scan lines and the similarity of the functions, rather than the use of ROM 117 to store two full scan lines of 4.21 MHz sine and cosine waves. We will distinguish them except for deviations in the time base to reduce To generate an address for the ROM that stores the 4.21 MHz sine and cosine function half scan lines for the purpose of generating a 4.21 MHz carrier with the correct phase for each scan line, and to control that the ROM output signal is selectively negative. The three upper bits of the bit's write address are used to control the modification of the lower nine bits of the 12 bit's write address. In the claims appended hereto, such alternative devices are described within the scope of the term read-only memory.

4 and 5 show that the reset value of the write address counter 23 is used as the coefficient input signal of the scan line counter 113, and for the purposes of the present invention, the scan line counter 113 is used for counting modulo 4 of continuous horizontal scan lines. It just needs to be a binary counter. However, for other purposes a multi-stage binary counter can be used to accumulate higher coefficients of continuous scan lines or semi-scan lines, and two bits in the output signal of counter 113 are shown in FIG. 4 to control the programmable outlier 114. It can be used to provide a modulus of 4 coefficients of the desired scan line to be used, and the two bits can be used in FIG. 5 to address the ROM which stores the 4.21 MHz sine cosine lookup table. This multi-stage binary counter 113 should be in the form of counting the horizontal scan lines for two frame periods so that modulo 4 coefficients of successive horizontal scan lines are properly processed.

The reproduction apparatus of FIG. 6 receives the time multiplexed L + ID signal recovered from the recording medium by the method according to the prior art to recover the luminance signal, and the recording medium by the method according to the prior art to recover the color under signal. Receive the encoded chromaticity signal of the C + M color undersignal and the same signal C + M. Analog L + ID and analog C + M are digitized by a third analog-to-digital converter (ADC3) 513 and a fourth analog-digital converter (ADC4) 514, respectively, and the converters structure comprises a first analog-to-digital converter (ADC1) 13 and Similar to second analog-to-digital converter ADC2 14. The digitized L + ID signal is supplied to a third time base corrector 515 (TBC3) and the structure of the third time base corrector is similar to the first time base corrector 15 (TBC1). The digitized C + M signal is supplied to a fourth time base corrector 516 (TBC4) and the structure of the fourth time base corrector is similar to the second time base corrector 16 (TBC2). Thus, during regeneration, a switching device (not shown) is provided by using elements 13-16 as elements 513-516 rather than using separate elements 513-516.

The luminance signal reproduction circuit includes a third analog-digital converter 513 (ADC3), a third time base corrector 515 (TBC3), a luminance signal reproduction processor 540, an ID signal detector 550, and a multiplexer 551. Through a suitable switching device (not shown), the luminance signal recording processor 540 during reproduction may use the elements used in the luminance signal recording processor 40 during recording. The ADC 153 digitizes the reproduced luminance signal and the ID signal L + ID, and the TBC3 515 performs TBE correction on the digitized signal as a result. If the reproduced luminance signal is a non-standard signal or only the reproduced luminance signal is a non-standard signal, the ID signal detector 550 generates a control signal that is a condition of the multiplexer 551 to apply arithmetic 1 to the luminance signal reproducing processor 540, and the luminance signal Arithmetic 1 applied to the reproduction processor 540 becomes a condition of the luminance signal recording processor for generating the output signal L by spatial processing.

The luminance signal reproducing processor 540 includes an unfolder 546 for storing a luminance signal of which the bandwidth entered by frequency folding is reduced in the original frequency sideband of the luminance signal, and a time for removing the sidebands of the folding carrier and the unwanted image. A filter 541, a noise canceller 543, a soft switch 544, a copper factor generator 545, and a multiplexer 547 are provided for improving the image quality when the reproduced signal is recorded by a conventional VHS system. The output signal from the noise canceler 543 and the output signal from the soft switch 544 supplied as the input signal of the multiplexer 547 by the mode selection signal specifying the type of video signal to be played back from the tape, whether as a normal VHS system or a bandwidth reduction system. By selecting one of these, multiplexer 547 regenerates its output signal. In the same operation as the copper factor generator 45 of the luminance signal recording processor 400 described above, the driver factor generator operates in response to the input signal of the ID signal detector 550.

The chroma signal reproduction circuit includes a fourth analog-to-digital converter 514 (ADC4), a fourth time axis corrector 516 (TBC4), a stable four-phase 4.21 MHz carrier generator 519, and an uplink frequency converter 520. The ADC4 154 digitizes the reproduced copper and chromatic signals, while the TBC4 516 corrects the TBE while reproducing the digitized copper and chromatic signals. The copper / chromatic signal separator 517 separates the copper signal from the chroma signal, and the copper / chromatic signal separator 517 supplies the copper signal to the 551 multiplexer for selective application to the copper factor generator 545. The isolated chromaticity signal is converted to analog form by the digital-to-analog converter 518 to be applied to the input of the up-converter 520 and 3.58 MHz from a frequency of 629 KHz according to the stable 4.21 MHz clock signal provided by the 4.21 MHz carrier generator 519. The frequency is uplinked to frequency. The 4.21 MHz carrier generator 519 supplies a stable 4.21 MHz clock with four phases with phase shift from one horizontal scan line to the next horizontal scan line during reproduction. This phase shift is heterodyne with the phase shift of the 629 KHz color undercarrier from one scan line to the next, thus removing this phase shift within the sideband of the regenerated 3.58 MHz chroma signal provided from the uplink frequency converter 520. Thus, the line-to-line variation in the carrier phase adjustment of the regenerated 3.8 MHz chromaticity signal sidebands supplied from the uplink frequency converter 520 is the line-to-line variation of the carrier phase adjustment of the 3.58 MHz chromaticity signal sidebands in the composite signal originally supplied for recording. To repeat.

The regenerated 3.58 MHz chromaticity signal sidebands supplied from the uplink frequency converter 520 are combined in addition to the luminance signal L supplied from the multiplexer 547 in a circuit subsequent to that shown in FIG. There is usually a filtering process that precedes the addition combining process for regenerating the composite video signal. The composite video signal is used to combine the modulated sound carriers and then modulate the low level radio frequency carriers. Modulated radio frequency carriers are suitable for application in color television receivers.

7 shows one form that a stable 4.21 MHz carrier generator 519 can have, and the time base compensator TBC4 used for playback takes the form of using the same lead address generator 30 used for the time base compensator TBC2 during recording. The lead address generator 30 includes a lead address generator 33. The lead address counter 33 is a 10.1 MHz supply from the VCO 32 to the carry-in connection of the 4-stage binary counter 331 to generate a 629 KHz square wave at the carry-out (CO) connection of the 4-stage binary counter 331. Four-stage binary counter 331 for counting the vibrations of the two stages, and 6-stage two for counting 629 KHz square wave supplied from the carry-out connection of the four-stage binary counter 331 to the carry-in connection of the six-stage binary counter 331. It is further equipped with a true counter 331 and a decoder 333 responsive to the combined coefficients of the counter 331 and the counter 332 to reset to 00 0000 0000 after the combined coefficients of the counter 331 and the counter 332 reach 10 0111 1111. It is showing.

The stable 4.21 MHz clock generator 60 is an amplifier 61 that receives 629 KHz square wave from the carry-out (CO) connection of the four-stage binary counter 331 as an input signal, and generates a very stable 3.58 MHz sine wave over time. A crystal oscillator 62, a counter 63 for counting modulo 4 of the horizontal scanning line, a programmable idealizer 64 for shifting a 3.58 MHz sine wave by 90 ° according to the modulo 4 coefficient, and a 3.58 MHz phase shifted from the ideal phase 64 It is further shown that it has an uplink frequency converter 65 that generates a stable 4.21 MHz clock frequency in response to the sum frequency of the sine wave oscillation and the amplified 629 KHz output signal of amplifier 61. The 629 KHz output signal is a phase locked loop PLL1. It is stable because of the length of the time constant τ ₂ . Programmable idealizer 64 makes the phase shift of the stable 4.21 MHz clock and the phase shift of the 629 KHz color undersignal heterodyne from one scan line to the next, even during playback, as introduced during recording, so this phase shift is uplink frequency converter 520 Is compensated for in the output signal.

8 shows another form that a stable 4.21 MHz carrier generator 519 can have, and the time base compensator TBC4 used in playback takes the form of using the same lead address generator 30 used for the time base compensator TBC2 in recording. The lead address counter 33 has a structure substantially the same as that described with respect to FIG. The scan line counter 63 also has a structure substantially the same as that described in FIG. Read-only memory 67 stores sine and cosine wave lookup tables, and digital-to-analog converter 68 converts the lead signal from ROM 67 into analog form for application to the uplink frequency converter 520 of FIG. The lookup table in ROM 67 is selected sequentially for the lead and this selection takes place according to the modulo 4 coefficients of the horizontal scan line supplied from the scan line counter 63. This selection is intended to introduce a phase shift of the 4.21 MHz clock that heterodynes the phase shift of the 629 KHz color under signal from one scan line to the next during playback, as in video recording. It is removed within the sideband of the supplied 3.58 MHz chroma signal.

FIG. 9 still shows another form that the stable 4.21 MHz signal generator of FIG. 6 may have, which is similar to that used in a conventional VHS video recorder playback apparatus. Although not as simple as the stable 4.21 MHz generator of FIGS. 7 and 8, fast-forward, frame-freeze or other technical methods are better controlled. The analog color undersignal from the digital-to-analog converter 518 and the stable four-phase 4.21 MHz clock generated are heterodyne in mixer 601. The sidebands of the 3.58 MHz signal with phase adjustment to suit the composite video signal are separated by band pass filters that suppress high frequency video signals. Buster gate 603 selects a color buster from the sideband of the 3.58 MHz signal and sends it to phase detector 604, which detects an error in the buster separated from the 3.58 MHz vibration supplied from crystal oscillator 610 (generating 3.58 MHz vibration). This is because crystal oscillators are widely used in color television receivers, and such crystal oscillators are relatively inexpensive and are commonly used as a time base reference for servomechanisms that control tape speeds. Passed through a low pass filter 605 with a time constant τ ₃ of duration and then input as a control signal to a voltage controlled 629 KHz oscillator, the voltage controlled 629 KHz oscillator 606 receives a four phase carrier of the color undersignal. 4 phase 629 KHz vibration and crystal oscillator 610 supplied to oscillator 606. Single-phase 3.58 MHz oscillations are heterodyne in mixer 607 to generate a four-phase 2.95 MHz signal and a 4.21 MHz carrier, and bandpass filter 608 selects a four-phase 4.21 MHz carrier as a stable 4.21 MHz signal for application to mixer 601. The degenerative feedback loop formed by interconnected elements 601-608 removes the line-to-line phase modulation applied during video recording from the color burst signal accompanying the sideband of the 3.58 MHz chroma signal at playback.

Many variations on the design of the phase locked loop are well known to those of ordinary skill in the phase locked loop design and could be used as alternative embodiments of the present invention. For example, the output of the address counter may be latched in response to a repetitive edge of the horizontal sync pulse to generate an error signal for the VCO whose frequency is counted by the address counter as a substantially digitized sawtooth wave. As another example, the above-described form of a phase locked loop may be modified to use a digitized sawtooth wave from an address counter for addressing a read only memory, where the read only memory has an error for a VCO whose frequency is counted. It stores the characteristics of a discriminator with a very steep inclination latched in response to the repeated edge of the horizontal sync pulse to generate a signal. As another example, the digital discriminator response may be converted to analog form, and a horizontal sync pulse may be used to gate the analog discriminator response for generating an error signal for the VCO whose vibration is counted. Many other variations are known in phase locked loop designs.

Mixers 12 and 520 are each disclosed in such a way that the difference of the heterodyne signals is selected by the mixer output filtering to be the output signal of the mixer. Instead, mixers of the form in which the sum of the heterodyne signals are selected by the output filtering of the mixer are used in other video recording / reproducing systems embodying the spirit of the present invention, where the 4.21 MHz carrier is used as the carrier at 2.95 MHz. Replaced. However, this indicates a departure from the standard VHS approach.

Videotape recorders, in which the generation of color undersignals are carried out completely or substantially in a digital system, can embody the invention in a broader aspect. Although the present invention has been described with particular reference to the processing of folded spectral luminance signals regarding time-base correction of separately recorded luminance and chromaticity signals, TBCs for separately recorded luminance and chromaticity signals are generally used in video recording / reproducing systems. There is general applicability in video recording / reproducing systems which can be applied and where digital processing of luminance signals or chromatic signals or both is performed and requires time-base stability.

Claims (9)

A video recorder for recording a composite video signal using color under signals, comprising: a separator for separating horizontal sync information from the composite video signal being recorded; Means for separating the chromaticity information region of the composite video signal being recorded; An analog to digital converter for digitizing samples of the composite video signal being recorded; A downlink frequency converter for generating a color under signal by mixing the separated chromaticity information and the non-carrier signal; Control for generating a continuous pixel clock signal whose frequency and phase are determined based on the oscillator control signal at a predetermined ratio, wherein the ratio is at least twice the frequency of the analog sine wave and the sampling rate is set by the analog-to-digital converter. oscillator; A counter for counting the number of pixel clock signals provided by the control oscillator, comprising means for counting the number of pixels occurring in the four scan lines and then returning the coefficients to an initial value; A frequency divider for dividing a coefficient of the counter by a predetermined factor to generate a divisor of the coefficient from the counter; A discriminator for discriminating when a divisor of the coefficients derived from the counter differs in frequency or phase from horizontal sync information separated from the composite video signal to be recorded for making an error signal; A low pass filter for generating the error signal in response to the oscillator control signal, forming a connected phase locked loop comprising the control oscillator, the counter, the frequency divider, the discriminator and a low pass filter; And means for responding to a condition of the counter to derive the non-carrier signal. 2. The apparatus of claim 1, wherein the means for generating the non-carrier signal is provided as a table lookup address signal to a table lookup circuit for generating a continuous digital signal sample of the non-carrier signal. A table lookup circuit responsive to the resulting non-divided address coefficients; And a digital-to-analog converter for converting the continuous digital sample of the non-carrier signal into a continuous analog form applied to the downlink frequency converter for mixing with the separated chromaticity. 3. The apparatus of claim 2, wherein the table lookup circuit comprises a read only memory. 3. The apparatus of claim 2, wherein the table lookup circuit comprises only a read only memory. 3. The apparatus of claim 2, wherein the continuous analog form of the non-verse carrier applied to the downlink frequency converter is a continuous sinusoidal signal having a frequency of 4.21 MHz. 3. The apparatus of claim 2, wherein the continuous analog form of the non-verse carrier applied to the downlink frequency converter is a continuous sinusoidal signal having a frequency of 2.95 MHz. 2. The apparatus of claim 1, wherein the means for generating a non-carrier signal comprises: an oscillator oscillating at a suppressed carrier frequency of a chromaticity information region of a composite video signal to be recorded; Means for deriving 4 from a counter of the counter to a horizontal scan line counting module; The four phases controlled by coefficient modulo 4 of the horizontal scan line to provide a corresponding one of the vibrations of the four phases derived from the oscillator oscillating at the suppressed carrier frequency of the chromaticity information region of the composite video signal to be recorded. Means for varying by 90 ° as the four phases are successively selected by modulo 4 of the increasing horizontal scan line to oscillate the mixed signal; Means for dividing a coefficient of the counter to generate a square wave at a suppressed carrier frequency of the color under signal; And an uplink frequency converter for mixing the non-carrier signal with the mixing signal and the square wave. 8. The apparatus of claim 7, wherein the non-verse signal applied to the downlink frequency converter is an analog sine wave signal having a frequency of 4.21 MHz. 8. The apparatus of claim 7, wherein the non-verse signal applied to the downlink frequency converter is an analog sine wave signal having a frequency of 2.95 MHz.