JPS62155528U

JPS62155528U -

Info

Publication number: JPS62155528U
Application number: JP4297786U
Authority: JP
Priority date: 1986-03-26
Filing date: 1986-03-26
Publication date: 1987-10-02

Description

[Brief explanation of the drawing]

第１図乃至第４図はこの考案の一実施例を示す
もので、第１図はＰＬＬ全体の回路構成を示す図
、第２図は第１図の特に位相比較回路の回路構成
を詳細に示す図、第３図は第２図のアナログスイ
ツチの回路構成例を示す図、第４図は位相比較回
路での入出力信号の波形を示す図、第５図はＰＬ
Ｌ回路の基本の回路構成を示すブロツク図、第６
図乃至第９図は従来の位相比較回路を示す図で、
第６図はデジタル位相比較回路の構成を示す図、
第７図は第６図の入出力信号の波形を示す図、第
８図はアナログ位相比較回路の構成を示す図、第
９図は第８図の入出力信号の波形を示す図である
。１１，１５，１６，２１……位相比較回路、１
２，２２……ローパスフイルタ、１３，２３……
ＶＣＯ、１４，２４……分周回路、２０……ＬＳ
Ｉ、２１ａ……アナログスイツチ、２１ａ１〜２
１ａ９……ＦＥＴ、２３ａ……可変容量コンデン
サ、２３ｆ……インバータ。 Figures 1 to 4 show an embodiment of this invention, with Figure 1 showing the overall circuit configuration of the PLL, and Figure 2 showing the circuit configuration of Figure 1, especially the phase comparator circuit, in detail. FIG. 3 is a diagram showing an example of the circuit configuration of the analog switch in FIG. 2, FIG.
Block diagram showing the basic circuit configuration of the L circuit, No. 6
9 to 9 are diagrams showing conventional phase comparator circuits,
FIG. 6 is a diagram showing the configuration of a digital phase comparator circuit,
7 is a diagram showing the waveforms of the input/output signals in FIG. 6, FIG. 8 is a diagram showing the configuration of the analog phase comparison circuit, and FIG. 9 is a diagram showing the waveforms of the input/output signals in FIG. 8. 11, 15, 16, 21...phase comparison circuit, 1
2, 22...Low pass filter, 13, 23...
VCO, 14, 24... Frequency divider circuit, 20... LS
I, 21a...Analog switch, 21a1-2
1a9...FET, 23a...variable capacitor, 23f...inverter.

Claims

[Claim for Utility Model Registration] In a PLL circuit that oscillates a reference clock used in LCD television equipment, etc., the PLL circuit closes in response to a horizontal synchronizing signal obtained from a TV broadcast signal, and transmits a clock pulse sent from a frequency dividing circuit. An analog switch is connected to the output terminal of this analog switch to pass it as an error signal to the next low-pass filter, and the applied voltage is divided by resistance, and when the analog switch is open, a DC voltage of a specific level is passed to the next stage. 1. A PLL circuit comprising a phase comparator circuit having a dividing resistor that outputs an error signal to a low-pass filter in a stage.