JPS6059631U - Phase-lock droop circuit - Google Patents
Phase-lock droop circuitInfo
- Publication number
- JPS6059631U JPS6059631U JP14964583U JP14964583U JPS6059631U JP S6059631 U JPS6059631 U JP S6059631U JP 14964583 U JP14964583 U JP 14964583U JP 14964583 U JP14964583 U JP 14964583U JP S6059631 U JPS6059631 U JP S6059631U
- Authority
- JP
- Japan
- Prior art keywords
- output
- terminal
- voltage element
- level
- potential point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
′ 第1図は従来回路を説明する回路図、第2図はその
動作を説明するためのタイムチャート、第3図はこの考
案の一実施例を示す回路図、第4図は第3図に示した実
施例のレベル変換器の詳細を示す回路図、第5図は第3
図に示す実施例の動作を説明するためのタイムチャート
である。
1・・・ディジタル位相比較器、2・・・低域フィルタ
、3・・・増幅器、4・・・電圧制御発振器、5・・・
分周器、6・・・レベル変換器。
第1図
第5図' Fig. 1 is a circuit diagram explaining the conventional circuit, Fig. 2 is a time chart to explain its operation, Fig. 3 is a circuit diagram showing an embodiment of this invention, and Fig. 4 is similar to Fig. 3. A circuit diagram showing details of the level converter of the embodiment shown, FIG.
3 is a time chart for explaining the operation of the embodiment shown in the figure. DESCRIPTION OF SYMBOLS 1...Digital phase comparator, 2...Low pass filter, 3...Amplifier, 4...Voltage controlled oscillator, 5...
Frequency divider, 6...level converter. Figure 1 Figure 5
Claims (2)
較するディジタル位相比較器と、このディジタル位相比
較器の出力電圧をレベル変換するレベル変換器と、この
レベル変換回路の出力の高周波成分を遮断する低域フィ
ルタと、この低域フィルタの出力を増幅する増幅器と、
この増幅器の出力により発振周波数が制御される電圧制
御発振器と、この電圧制御発振器の出力を分周し、得ら
れる分周信号を前記ディジタル位相比較器に帰還信号と
して出力する分周器とを具備することを特徴とするフェ
ーズロックドルーフ回路。(1) A digital phase comparator that compares the phases of a clock signal of a predetermined frequency and a feedback signal, a level converter that converts the level of the output voltage of this digital phase comparator, and a high-frequency component of the output of this level conversion circuit that is cut off. a low-pass filter that amplifies the output of the low-pass filter;
It is equipped with a voltage controlled oscillator whose oscillation frequency is controlled by the output of this amplifier, and a frequency divider which divides the output of this voltage controlled oscillator and outputs the obtained frequency-divided signal to the digital phase comparator as a feedback signal. A phase-locked roof circuit characterized by:
入力とする定電圧素子と、この定電圧素子の入力端子と
基準電位点との間に介挿された第1の抵抗と、前記定電
圧素子の出力端子と所定電位点との間に介挿された可変
抵抗と、ベース端子を前記定電圧素子の出力端子に接続
し、コレクタ端子を前記基準電位点に接続し、エミッタ
端子をレベル変換器の出力端子としたトランジスタと、
前記エミッタ端子と前記所定電位点との間に介挿された
第2の抵抗とからなることを特徴とする実用新案登録請
求の範囲第(1)項記載、のフェーズロックドルーフ回
路。(2) The level converter consists of a constant voltage element that receives the output of the digital phase comparator, a first resistor inserted between the input terminal of the constant voltage element and a reference potential point, and the constant voltage element. A variable resistor is inserted between the output terminal of the voltage element and a predetermined potential point, the base terminal is connected to the output terminal of the constant voltage element, the collector terminal is connected to the reference potential point, and the emitter terminal is connected to the level. A transistor used as the output terminal of the converter,
The phase-locked roof circuit according to claim 1, characterized in that the circuit comprises a second resistor inserted between the emitter terminal and the predetermined potential point.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14964583U JPS6059631U (en) | 1983-09-29 | 1983-09-29 | Phase-lock droop circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14964583U JPS6059631U (en) | 1983-09-29 | 1983-09-29 | Phase-lock droop circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6059631U true JPS6059631U (en) | 1985-04-25 |
Family
ID=30332126
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14964583U Pending JPS6059631U (en) | 1983-09-29 | 1983-09-29 | Phase-lock droop circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6059631U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0364126A (en) * | 1989-07-31 | 1991-03-19 | Sharp Corp | Phase locked loop oscillation circuit |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5212548A (en) * | 1975-07-21 | 1977-01-31 | Seikosha Co Ltd | Indicating device of action fluctuation of an oscillator |
JPS5374874A (en) * | 1976-12-13 | 1978-07-03 | Texas Instruments Inc | Current controlled ring oscillator and frequency synthesizer utilizing same |
-
1983
- 1983-09-29 JP JP14964583U patent/JPS6059631U/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5212548A (en) * | 1975-07-21 | 1977-01-31 | Seikosha Co Ltd | Indicating device of action fluctuation of an oscillator |
JPS5374874A (en) * | 1976-12-13 | 1978-07-03 | Texas Instruments Inc | Current controlled ring oscillator and frequency synthesizer utilizing same |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0364126A (en) * | 1989-07-31 | 1991-03-19 | Sharp Corp | Phase locked loop oscillation circuit |
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