JPS5927639U - Phase throttle loop circuit - Google Patents

Phase throttle loop circuit

Info

Publication number
JPS5927639U
JPS5927639U JP12356182U JP12356182U JPS5927639U JP S5927639 U JPS5927639 U JP S5927639U JP 12356182 U JP12356182 U JP 12356182U JP 12356182 U JP12356182 U JP 12356182U JP S5927639 U JPS5927639 U JP S5927639U
Authority
JP
Japan
Prior art keywords
voltage
phase
loop circuit
phase difference
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12356182U
Other languages
Japanese (ja)
Inventor
安島　秀延
Original Assignee
パイオニア株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パイオニア株式会社 filed Critical パイオニア株式会社
Priority to JP12356182U priority Critical patent/JPS5927639U/en
Publication of JPS5927639U publication Critical patent/JPS5927639U/en
Pending legal-status Critical Current

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図はフェイズロックループ回路の従来例を示す回路
図、第２図は本考案のフェイズロックループ回路の実施
例を示す回路図である。 主要部分の符号の説明、１・・・・・・ＶＣｏ、　２・
・・・・・分周器、３・・・・・・位相比較器。、４・
・・・・・ループフィルタ回路。FIG. 1 is a circuit diagram showing a conventional example of a phase-locked loop circuit, and FIG. 2 is a circuit diagram showing an embodiment of the phase-locked loop circuit of the present invention. Explanation of symbols of main parts, 1...VCo, 2.
...Frequency divider, 3...Phase comparator. , 4・
...Loop filter circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力電圧レベルに応じた周波数の発振信号を発生する電
圧制御発振手段と、前記発振信号と所定周波数の基準信
号との位相差の大きさに応じた位相差信号を発生する位
相比較手段と、前記位相差信号に応じたレベルの直流電
圧を前記電圧制御発振手段に供給するループフィルタ手
段とを含み、前記ループフィルタ手段は出力電圧の最小
値を所定レベル以上に保持する分圧抵抗器を有すること
を特徴とするフェイズロックループ回路。voltage-controlled oscillation means for generating an oscillation signal with a frequency corresponding to an input voltage level; phase comparison means for generating a phase difference signal according to the magnitude of the phase difference between the oscillation signal and a reference signal of a predetermined frequency; loop filter means for supplying the voltage controlled oscillation means with a DC voltage at a level corresponding to the phase difference signal, and the loop filter means has a voltage dividing resistor that maintains the minimum value of the output voltage at a predetermined level or higher. A phase-locked loop circuit featuring:
JP12356182U 1982-08-13 1982-08-13 Phase throttle loop circuit Pending JPS5927639U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12356182U JPS5927639U (en) 1982-08-13 1982-08-13 Phase throttle loop circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12356182U JPS5927639U (en) 1982-08-13 1982-08-13 Phase throttle loop circuit

Publications (1)

Publication Number Publication Date
JPS5927639U true JPS5927639U (en) 1984-02-21

Family

ID=30282007

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12356182U Pending JPS5927639U (en) 1982-08-13 1982-08-13 Phase throttle loop circuit

Country Status (1)

Country Link
JP (1) JPS5927639U (en)

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