JPS6085442U - phase synchronized circuit - Google Patents

phase synchronized circuit

Info

Publication number
JPS6085442U
JPS6085442U JP17697183U JP17697183U JPS6085442U JP S6085442 U JPS6085442 U JP S6085442U JP 17697183 U JP17697183 U JP 17697183U JP 17697183 U JP17697183 U JP 17697183U JP S6085442 U JPS6085442 U JP S6085442U
Authority
JP
Japan
Prior art keywords
frequency
phase
output
voltage
phase synchronized
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17697183U
Other languages
Japanese (ja)
Inventor
憲二 佐藤
藤本 尚延
村勢 徹郎
岩崎 雅明
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP17697183U priority Critical patent/JPS6085442U/en
Publication of JPS6085442U publication Critical patent/JPS6085442U/en
Pending legal-status Critical Current

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の位相同期回路を示す図、第2図、第3図
はそのタイムチャート、第4図は本考案の一実施例を示
す図である。 図中FF工〜FF3はフリップフロップ、vCOは電圧
制御発振器、TIMはタイマである。
FIG. 1 is a diagram showing a conventional phase synchronization circuit, FIGS. 2 and 3 are time charts thereof, and FIG. 4 is a diagram showing an embodiment of the present invention. In the figure, FF~FF3 are flip-flops, vCO is a voltage controlled oscillator, and TIM is a timer.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電圧制御発振器出力と入力信号の位相を比較し、その出
力により該電圧制御発振器の発振周波数を制御する様に
した位相同期回路において、該電圧制御発振器出力を分
周する第1分周器と、該入力信号を分周する第2分周器
と、該入力信号断時該分周器出力をいずれか一方のレベ
ルに固定する制御回路を設けたことを特徴とする位相同
期回路。
In a phase-locked circuit that compares the phase of a voltage-controlled oscillator output and an input signal, and controls the oscillation frequency of the voltage-controlled oscillator using the output thereof, a first frequency divider that divides the frequency of the voltage-controlled oscillator output; A phase synchronized circuit comprising: a second frequency divider that divides the frequency of the input signal; and a control circuit that fixes the output of the frequency divider to one of the levels when the input signal is interrupted.
JP17697183U 1983-11-16 1983-11-16 phase synchronized circuit Pending JPS6085442U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17697183U JPS6085442U (en) 1983-11-16 1983-11-16 phase synchronized circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17697183U JPS6085442U (en) 1983-11-16 1983-11-16 phase synchronized circuit

Publications (1)

Publication Number Publication Date
JPS6085442U true JPS6085442U (en) 1985-06-12

Family

ID=30384600

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17697183U Pending JPS6085442U (en) 1983-11-16 1983-11-16 phase synchronized circuit

Country Status (1)

Country Link
JP (1) JPS6085442U (en)

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