JPS59147344U - Receiving machine - Google Patents
Receiving machineInfo
- Publication number
- JPS59147344U JPS59147344U JP4076983U JP4076983U JPS59147344U JP S59147344 U JPS59147344 U JP S59147344U JP 4076983 U JP4076983 U JP 4076983U JP 4076983 U JP4076983 U JP 4076983U JP S59147344 U JPS59147344 U JP S59147344U
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- receiving machine
- local oscillator
- predetermined frequency
- steps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Superheterodyne Receivers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来の受信機の構成を示すブロック図。
第2図は本考案の一実施例の構成を示すブロック図。
4、 6. 8および316・・・混合器、5.7およ
び9・・・バンドパスフィルタ、11・・・第1の局部
発振器、13・・・第3の局部発振器、21・・・4逓
倍器、111.112.311および315・・・分周
器、113および312・・・VCo、114および
′313・・・プログラマブル分周器、115およ
び314・・・位相比較器。FIG. 1 is a block diagram showing the configuration of a conventional receiver. FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention. 4, 6. 8 and 316...mixer, 5.7 and 9...bandpass filter, 11...first local oscillator, 13...third local oscillator, 21...4 multiplier, 111 .112.311 and 315... Frequency divider, 113 and 312... VCo, 114 and
'313...Programmable frequency divider, 115 and 314...Phase comparator.
Claims (1)
LL回路からなる周波数のシンセサイザで構成されかつ
受信周波数を第1の所定周波数幅のステップで変化させ
る第1の局部発振器と、前記第1のPLL回路から独立
した第2のPLL回路からなる周波数シンセサイザで構
成されかつ前記第1の所定周波数幅内の周波数を第2の
所定周波数幅のステップで変化させる第3の局部発振器
とを備えてなることを特徴とする受信機。In a triple conversion type receiver, the first P
A frequency synthesizer consisting of a first local oscillator consisting of a frequency synthesizer consisting of an LL circuit and changing the received frequency in steps of a first predetermined frequency width, and a second PLL circuit independent of the first PLL circuit. and a third local oscillator configured to change the frequency within the first predetermined frequency width in steps of a second predetermined frequency width.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4076983U JPS59147344U (en) | 1983-03-23 | 1983-03-23 | Receiving machine |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4076983U JPS59147344U (en) | 1983-03-23 | 1983-03-23 | Receiving machine |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59147344U true JPS59147344U (en) | 1984-10-02 |
Family
ID=30171382
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4076983U Pending JPS59147344U (en) | 1983-03-23 | 1983-03-23 | Receiving machine |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59147344U (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05129843A (en) * | 1991-10-31 | 1993-05-25 | Dx Antenna Co Ltd | Retransmitting single channel signal processor |
JP2006229404A (en) * | 2005-02-16 | 2006-08-31 | Nec Corp | Double frequency converter |
-
1983
- 1983-03-23 JP JP4076983U patent/JPS59147344U/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05129843A (en) * | 1991-10-31 | 1993-05-25 | Dx Antenna Co Ltd | Retransmitting single channel signal processor |
JP2006229404A (en) * | 2005-02-16 | 2006-08-31 | Nec Corp | Double frequency converter |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS59147344U (en) | Receiving machine | |
JPS5811342U (en) | Phase-locked frequency synthesizer | |
JPS5929812U (en) | FM modulation circuit | |
JPS58176414U (en) | FM demodulation circuit | |
JPS5956859U (en) | PLL channel selection device | |
JPS6068742U (en) | automatic frequency control circuit | |
JPS5850534U (en) | PLL circuit | |
JPS6352316U (en) | ||
JPS635730U (en) | ||
JPS5929813U (en) | Structure of frequency modulation circuit | |
JPS60103949U (en) | frequency synthesizer | |
JPS59169149U (en) | Receiving machine | |
JPS58123635U (en) | Receiving machine | |
JPS58164342U (en) | frequency synthesizer | |
JPS58152035U (en) | phase locked loop | |
JPS5849285U (en) | timer clock circuit | |
JPS60193720U (en) | PLL circuit | |
JPS58189632U (en) | frequency synthesizer | |
JPS5984934U (en) | phase locked loop | |
JPS59177246U (en) | Double conversion type receiver | |
JPS6019238U (en) | FM signal generator | |
JPS60132038U (en) | PLL circuit | |
JPS62159029U (en) | ||
JPS5873652U (en) | phase locked loop circuit | |
JPS5843044U (en) | frequency synthesizer |