JPS5850534U - PLL circuit - Google Patents

PLL circuit

Info

Publication number
JPS5850534U
JPS5850534U JP14558181U JP14558181U JPS5850534U JP S5850534 U JPS5850534 U JP S5850534U JP 14558181 U JP14558181 U JP 14558181U JP 14558181 U JP14558181 U JP 14558181U JP S5850534 U JPS5850534 U JP S5850534U
Authority
JP
Japan
Prior art keywords
pll circuit
oscillator
mixer
output
interpolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14558181U
Other languages
Japanese (ja)
Inventor
裕 服部
Original Assignee
株式会社ケンウッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社ケンウッド filed Critical 株式会社ケンウッド
Priority to JP14558181U priority Critical patent/JPS5850534U/en
Publication of JPS5850534U publication Critical patent/JPS5850534U/en
Pending legal-status Critical Current

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のＰＬＬ回路を示すブロック図、第２図は
本考案に係るＰＬＬ回路の実施例を示すブロック図であ
る。 １・・・逓降器、Ｏ８１・・・補間発振器、Ｓ・・・基
準発振器、Ｔ１．　Ｔ２・・・逓倍器、Ｍｌ、　Ｍ２・
・・ミクサ。FIG. 1 is a block diagram showing a conventional PLL circuit, and FIG. 2 is a block diagram showing an embodiment of the PLL circuit according to the present invention. 1...Downloader, O81...Interpolation oscillator, S...Reference oscillator, T1. T2...multiplier, Ml, M2・
...Mixa.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 補間発振器からの出力と基準発振器からの出力とを混合
してＰＬＬループ内のミクサに供給するように構成され
ているＰＬＬ回路に於いて、前記補間発振器と混合器と
の間に逓降器が設けらた、前記補間発振器の周波数変動
に伴うＰ−ＬＬ発振周波数の変動を低減させるように構
成されていることを特徴とするＰＬＬ回路。In a PLL circuit configured to mix an output from an interpolation oscillator and an output from a reference oscillator and supply the mixture to a mixer in a PLL loop, a down-stepper is provided between the interpolation oscillator and the mixer. A PLL circuit, characterized in that the PLL circuit is configured to reduce fluctuations in the P-LL oscillation frequency due to frequency fluctuations of the interpolation oscillator.
JP14558181U 1981-09-30 1981-09-30 PLL circuit Pending JPS5850534U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14558181U JPS5850534U (en) 1981-09-30 1981-09-30 PLL circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14558181U JPS5850534U (en) 1981-09-30 1981-09-30 PLL circuit

Publications (1)

Publication Number Publication Date
JPS5850534U true JPS5850534U (en) 1983-04-05

Family

ID=29938508

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14558181U Pending JPS5850534U (en) 1981-09-30 1981-09-30 PLL circuit

Country Status (1)

Country Link
JP (1) JPS5850534U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61111348U (en) * 1984-12-27 1986-07-14

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61111348U (en) * 1984-12-27 1986-07-14
JPH0313228Y2 (en) * 1984-12-27 1991-03-27

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