JPS60167427U - Noise removal circuit - Google Patents

Noise removal circuit

Info

Publication number
JPS60167427U
JPS60167427U JP5372084U JP5372084U JPS60167427U JP S60167427 U JPS60167427 U JP S60167427U JP 5372084 U JP5372084 U JP 5372084U JP 5372084 U JP5372084 U JP 5372084U JP S60167427 U JPS60167427 U JP S60167427U
Authority
JP
Japan
Prior art keywords
output
phase
low
pass filter
locked loop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5372084U
Other languages
Japanese (ja)
Inventor
茂 斉藤
Original Assignee
カルソニックカンセイ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by カルソニックカンセイ株式会社 filed Critical カルソニックカンセイ株式会社
Priority to JP5372084U priority Critical patent/JPS60167427U/en
Publication of JPS60167427U publication Critical patent/JPS60167427U/en
Pending legal-status Critical Current

Links

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Filters And Equalizers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の雑音除去回路を示す回路図、第2図はこ
の考案による雑音除去回路の一実施例を示す回路図であ
る。 1・・7入力端、2・・・リミッタ、3・・・位相ロッ
クループ回路、4・・・位相比較器、5・・・低域フィ
ルタ、6・・・電圧制御発振器、7・・・出力端。
FIG. 1 is a circuit diagram showing a conventional noise removal circuit, and FIG. 2 is a circuit diagram showing an embodiment of the noise removal circuit according to this invention. 1...7 input end, 2...limiter, 3...phase locked loop circuit, 4...phase comparator, 5...low pass filter, 6...voltage controlled oscillator, 7... Output end.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力端1と出力端7との間に介挿され、かつ前記入力端
1に供給される入力信号の周波数と前記出力端7から出
力される出力信号の周波数との位相差を検出しその位相
差に応じたパルス幅のパルスを出力する位相比較器4と
、該位相比較器4からの出力パルスを平滑して直流電圧
を出力する低域フィルタ5と、該低域フィルタ5からの
出力電圧によ、つて発振周波数が制御されその発振出力
が前記出力端7に接続された電圧制御発振器6とか、 
 らなる位相ロックループ回路3を備え、該位相ロック
ループ回路3の低域フィルタ5はその遮断周波数が十分
低く設定されてなることを特徴とする雑音除去回路。
The phase difference between the frequency of the input signal inserted between the input terminal 1 and the output terminal 7 and supplied to the input terminal 1 and the frequency of the output signal output from the output terminal 7 is detected and the phase difference is detected. A phase comparator 4 that outputs a pulse with a pulse width corresponding to the phase difference, a low-pass filter 5 that smoothes the output pulse from the phase comparator 4 and outputs a DC voltage, and an output voltage from the low-pass filter 5. a voltage controlled oscillator 6 whose oscillation frequency is controlled and whose oscillation output is connected to the output terminal 7;
1. A noise removal circuit comprising a phase-locked loop circuit 3 comprising a phase-locked loop circuit 3, wherein a low-pass filter 5 of the phase-locked loop circuit 3 has a cutoff frequency set sufficiently low.
JP5372084U 1984-04-12 1984-04-12 Noise removal circuit Pending JPS60167427U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5372084U JPS60167427U (en) 1984-04-12 1984-04-12 Noise removal circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5372084U JPS60167427U (en) 1984-04-12 1984-04-12 Noise removal circuit

Publications (1)

Publication Number Publication Date
JPS60167427U true JPS60167427U (en) 1985-11-07

Family

ID=30574846

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5372084U Pending JPS60167427U (en) 1984-04-12 1984-04-12 Noise removal circuit

Country Status (1)

Country Link
JP (1) JPS60167427U (en)

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