JPH0554759B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Industrial Application Field The present invention is suitable for use in low frequency conversion of chroma signals in VTRs (video tape recorders).
Concerning PLL (phase locked loop) circuits, especially PLL caused by equivalent pulses and vertical synchronization pulses that have different pulse widths from horizontal synchronization pulses.
The purpose is to prevent the circuit from becoming out of synchronization.

(b) Conventional technology "NHK Home Video Technology" published by Japan Broadcasting Publishing Association on November 10, 1980, page 95, Figure 7-
24 describes a PLL circuit for obtaining an output signal synchronized with a composite synchronizing signal consisting of a horizontal synchronizing pulse, an equivalent pulse, and a vertical synchronizing pulse. Said
The PLL circuit consists of a VCO (voltage controlled oscillator) and
It includes a frequency dividing circuit that divides the frequency of the output signal of the VCO, and a phase comparison circuit that compares the composite synchronization signal with the output signal of the frequency dividing circuit and generates an error signal, and applies the error signal to the VCO. By doing so,
The oscillation frequency and phase of the VCO are made to match the frequency and phase of the horizontal synchronization pulse in the composite synchronization signal.

(C) Problems to be Solved by the Invention However, the composite synchronization signal contains an equivalent pulse whose pulse width is narrower than that of the horizontal synchronization pulse,
Since the vertical sync pulse has a wider pulse width than the horizontal sync pulse, when the VCO is phase-locked to the horizontal sync pulse, when the equivalent pulse or vertical sync pulse is applied to the phase comparison circuit, There is a drawback that an error signal is generated from the phase comparator circuit, and the oscillation frequency and phase of the VCO change. For example, the phase of the composite synchronizing signal consisting of horizontal synchronizing pulse A, equivalent pulse B, and vertical synchronizing pulse C as shown in Fig. 3 A and the signal shown in Fig. 3 B obtained by dividing the output signal of the VCO is When the comparison is made, the signal shown in Figure 3C is obtained at the output of the phase comparator circuit, but the positive and negative signal A' obtained with respect to the horizontal synchronizing pulse A becomes zero after passing through the low-pass filter, so it is not an error signal. However, the signal B' obtained for the equivalent pulse B becomes a negative error signal, and the signal C' obtained for the vertical synchronization pulse C becomes a positive error signal, so the PLL
There was a risk that the circuit would become out of synchronization.

By the way, by using a circuit that combines a differential circuit and a slicer of a predetermined level, it is possible to compress a pulse with a wide pulse width, so if the composite synchronization signal shown in Fig. 3A is passed through the circuit, , the pulse width of the vertical synchronization pulse can be made approximately equal to the pulse width of the horizontal synchronization pulse. However, even if the circuit described above is used, it is not possible to extend the pulse width of the equivalent pulse, and the risk of the PLL circuit becoming out of synchronization still remains.

(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned points, and the present invention has been made in view of the above-mentioned points. A pulse shaping circuit is provided that expands the pulse width of the vertical synchronizing pulse in the composite synchronizing signal so that it is approximately equal to the pulse width of the horizontal synchronizing pulse, and compresses the pulse width of the vertical synchronizing pulse so that it becomes approximately equal to the pulse width of the horizontal synchronizing pulse. The feature is that the voltage is applied to the phase comparator circuit via the 2H killer circuit.

(E) Effect According to the present invention, since the pulse width of the pulse applied to the phase comparison circuit can be made substantially constant, the PLL circuit can be operated normally without malfunction.

(F) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention.
1 is a pulse shaping circuit having an input terminal 2 to which a composite synchronization signal is applied and a clock terminal 3 to which a clock pulse is applied; 4 deletes a part of the equivalent pulse contained in the output signal of the pulse shaping circuit 1; 1/2H killer circuit, 5 is a VCO having an oscillation frequency of 320H, 6 is a frequency dividing circuit that divides the output signal of the VCO 5 to 1/320, and 7 is the phase of the output signal of the 1/2H killer circuit 4. a phase comparison circuit that compares the phase of the output signal of the frequency dividing circuit 6 and generates an error signal;
and 8 is the output signal of the phase comparator circuit 7.
This is a loop filter for applying voltage to VCO5.

Input terminal 2 is supplied with a horizontal synchronizing pulse A having a predetermined pulse width as shown in FIG. A composite synchronization signal including pulse C is applied. and,
The composite synchronizing signal is shaped by a pulse shaping circuit 1, and at the output end of the pulse shaping circuit 1, a pulse train of pulses having a substantially constant pulse width as shown in FIG. 4B is obtained. The output signal of the pulse shaping circuit 1 is applied to a 1/2H killer circuit 4, and among the equivalent pulses and vertical synchronization pulses, those having a 1/2H period are deleted. Therefore, only pulses having a substantially constant pulse width of 1H period are generated at the output end of the 1/2H killer circuit 4. Said 1/2H killer circuit 4
The pulse obtained at the output of is applied to the phase comparator circuit 7, and the phase is compared with the output signal of the frequency divider circuit 6 shown in FIG. 4C. The phase comparator circuit 7 includes the 1/2
When the output signal of the H killer circuit 4 is "H" and the output signal of the frequency dividing circuit 6 is "L", the output is "L", and when the output signal of the 1/2H killer circuit 4 is "H", the frequency is divided. When the output signal of circuit 6 is “H”, the output “H” is
Since the output "0" is generated at other times, the output signal of the phase comparison circuit 7 is as shown in FIG. 4D. The output signal of FIG. 4D is then passed through the loop filter 8 as an error signal to the VCO.
5, the oscillation frequency and phase of the VCO 5 are controlled, and an output signal of 320H synchronized with the horizontal synchronizing pulse is obtained at the output terminal 9.

The pulse shaping circuit 1 is as shown in FIG. 2, and includes a first flip-flop circuit 11 that is set at the rising edge of each pulse of the composite synchronizing signal applied to the input terminal 10, and a Q of the first flip-flop circuit 11. a first AND gate 13 that ANDs the clock pulses applied to the output and the clock terminal 12; a counter 14 that counts the clock pulses obtained at the internal input terminal of the first AND gate 13;
A first decoder 15 that generates an output signal when the count of the counter 14 reaches a first predetermined value, and a second decoder 16 that generates an output signal when the count of the counter 14 reaches a second predetermined value. and a second AND gate 17 that generates a set signal according to the input pulse and the output signal of the first decoder 15.
and a second flip-flop circuit 18 which uses the output signal of the second AND gate 17 as a set signal and the output signal of the second decoder 16 as a reset signal.
, an input signal and the first flip-flop circuit 1
an OR gate 19 which takes an OR with the output of the first flip-flop circuit 11; a third AND gate 20 which takes an AND between the output signal of the OR gate 19 and the Q output of the first flip-flop circuit 11; Q output and a NOR gate that generates a reset signal for the counter 14 in response to the Q output.

When the horizontal synchronizing pulse A shown in FIG. 4A is applied to the input terminal 10, the first flip-flop 11 is set at the rising edge of the pulse A, and the Q output becomes "H". At this time, the second flip-flop circuit 18 has been reset and its output is "H", and the output of the OR gate 19 is "H", so the Q output of the first flip-flop circuit 11 is "H". When this happens, the output of the third AND gate 20 becomes "H", and the output signal rises simultaneously with the horizontal synchronizing pulse. When the Q output of the first flip-flop circuit 11 becomes "H", the clock pulse becomes "H".
The signal is applied to the counter 14 through the AND gate 13, and the counter 14 starts counting. When the count of the counter 14 advances and reaches a first predetermined value, the first decoder 15 generates an output signal.
The generation of the output signal from the first decoder 15 is as follows:
The time is set earlier than the fall of the horizontal synchronization signal and later than the fall of the equivalent pulse, so
When the output signal of the first decoder 15 is generated, the output of the second AND gate 17 becomes "H", and the second
Flip-flop circuit 18 is set. Therefore, the output of the second flip-flop circuit 18 becomes "L", but since the horizontal synchronization signal still exists, the output of the OR gate 19 continues to become "H".
The state of the output terminal 21 does not change. When more time passes and the horizontal synchronization signal falls, OR gate 1
9 becomes "L", and the third AND gate 20
Since the output also becomes "L", an output signal A' shown in FIG. 4B is obtained at the output terminal 21 in response to the horizontal synchronizing pulse A shown in FIG. 4A. When a certain amount of time has elapsed since the fall of the horizontal synchronizing signal and the value of the counter 14 reaches a second predetermined value, an output signal is generated from the second decoder 16, and the first and second flip-flop circuits 11 and 18 are activated. After being reset, the circuit of FIG. 2 returns to its initial state.

Next, the equivalent pulse B of FIG. 4A is applied to the input terminal 10.
When applied, the first flip-flop circuit 11 is set at the rising edge of the voltage, and the Q output becomes "H". At this time, the second flip-flop circuit 18 has been reset and its output is at "H", so the output terminal 21 becomes "H" in response to the rise of the equivalent pulse. Thereafter, even when the equivalent pulse falls, the output of the second flip-flop circuit 18 maintains "H" and the output of the OR gate 19 also maintains "H", so the output signal obtained at the output terminal 21 also remains "H". ” to maintain. When the Q output of the first flip-flop circuit 11 becomes "H", the counter 14 starts counting, and when the value of the counter 14 reaches a first predetermined value, the first decoder 15 generates an "H" output. At that point, the input signal is "L", so the second AND gate 1
No output is generated from the flip-flop circuit 8, and the second flip-flop circuit 18 is not set. When the count of the counter 14 progresses and reaches the second predetermined value, the second decoder 16
Since an "H" output is generated from the first flip-flop circuit 11 and the first flip-flop circuit 11 is reset, its Q output becomes "L" and the output of the third AND gate 20 also becomes "L". Therefore, the equivalent pulse B in FIG.
Accordingly, the output signal shown in Fig. 4B is output to the output terminal 21.
B' is obtained.

Furthermore, when the vertical synchronizing pulse C shown in FIG. 4A is applied to the input terminal 10, the first flip-flop circuit 11 is set at its rising edge, and the Q output becomes "H"
As in the case of equivalent pulse B, the output terminal 21
becomes “H”. Then, when the count of the counter 14 progresses and an "H" output is generated from the first decoder 15, the second AND gate 17 is set and the output of the second flip-flop circuit 18 becomes "L", but the input signal is "H". ” state is maintained,
The state of the output signal remains unchanged. When the value of the counter 14 reaches a second predetermined value and the output of the second decoder 16 becomes "H", the first and second flip-flop circuits 11 and 18 are reset, and the Q output of the first flip-flop circuit 11 is reset. Since it becomes "L", the output signal also becomes "L". Therefore, an output signal C' shown in FIG. 4B is obtained at the output terminal 21 in response to the vertical synchronizing pulse C in FIG. 4A. Therefore, by using the pulse shaping circuit shown in Fig. 2, an equivalent pulse with a narrower pulse width than the horizontal sync pulse and a vertical sync pulse with a wider pulse width than the horizontal sync pulse can be made to have approximately the same pulse width as the horizontal sync pulse. I can do it.

FIG. 5 shows a specific circuit example of the phase comparator circuit 7 in FIG. , 23 is a second input terminal to which the output signal of the 1/2H killer circuit 4 in FIG. 1 (waveform in FIG. 4 B) is applied, 24 is a NAND gate, 25 is an inverter,
6 is AND gate, 27 is P channel FET,
28 is an N-channel FET and 29 is an output terminal. If the first input terminal 22 is now "L" and the second input terminal 23 is "H", the P channel
The FET 27 is turned off, the N-channel FET 28 is turned on, and the output terminal 29 becomes "L". Further, if the first input terminal 22 is "H" and the second input terminal 23 is "H", the P channel FET 27 is turned on, the N channel FET 28 is turned off, and the output terminal 29 becomes "H". . Furthermore, in other cases, P channel FET27 and N channel
Both FETs 28 are turned off, and the output terminal 29 becomes "0". Therefore, by using the phase comparator circuit of FIG. 5, the output signal of FIG. 4D can be obtained from the input signals of FIG. 4B and C.

(g) Effects of the Invention As described above, according to the present invention, it is possible to provide a PLL circuit that can generate an output signal correctly synchronized with the horizontal synchronization signal in the composite synchronization signal. In particular, the
Since the PLL circuit is not adversely affected by the equivalent pulse or the vertical synchronization signal, the present invention can provide a stable PLL circuit that does not lose synchronization. Furthermore, as in the embodiment, if the falling edge of the horizontal synchronizing pulse is not affected by the quantization error of the counter, the stability of the PLL circuit can be further improved.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing a specific circuit example of the pulse shaping circuit, and Figs. 3 A to C are characteristic diagrams for explaining the conventional circuit. , FIGS. 4A to 4D are characteristic diagrams for explaining the present invention, and FIG. 5 is a circuit diagram showing a specific circuit example of the phase comparison circuit of FIG. 1. Explanation of main figure numbers, 1...Pulse shaping circuit, 5...
...VCO, 7...phase comparison circuit, 8...loop filter.

Claims (1)

[Claims] 1. An input terminal to which a composite synchronization signal is applied, a pulse shaping circuit connected to the input terminal, a 1/2H killer circuit connected to the output end of the pulse shaping circuit, a VCO, and the oscillation output of the VCO. Comparing the phases of a frequency dividing circuit that divides the signal, the output signal of the 1/2H killer circuit, and the output signal of the frequency dividing circuit,
The pulse shaping circuit includes a phase comparison circuit for generating an error signal and a loop filter for applying the error signal to the VCO, and the pulse shaping circuit includes a flip-flop set by the pulse of the composite synchronization signal, and a flip-flop that is set by the pulse of the composite synchronization signal. a counter that counts a clock signal of a predetermined frequency when the clock signal is set; a first decoder and a second decoder that detect that the counter has reached a first count value and a second count value; , when the pulse of the composite synchronization signal disappears before reaching the first count value, the pulse output is maintained, and when the pulse disappears between the first count value and the second count value, the composite synchronization signal is It is composed of a pulse generation circuit that outputs a signal pulse and stops the pulse output when the second count value is detected when a pulse exists after the second count value, and the pulse width of the equivalent pulse in the composite synchronization signal The PLL is characterized in that the pulse width of the vertical synchronization pulse in the composite synchronization signal is compressed so as to be approximately equal to the pulse width of the horizontal synchronization pulse. circuit.