JPS61189093A - Synchronous circuit - Google Patents

Abstract

PURPOSE:To obtain an excellent recovered clock signal with good noise immunity by adding a frequency synchronizing loop to a phase locked loop based on a burst only at asynchronous state in the reproducing synchronous circuit of a video tape recorder. CONSTITUTION:A burst gate 2 extracts a burst signal in an input signal, gives it to a voltage controlled type variable frequency oscillator 6 through a multiplier 3, an LPF 4 and an adder 5 to extract a clock signal at an output terminal 7. The clock signal is fed to the multiplier 3 via a 1/4 frequency divider 8 to constitute a phase locked loop 10. A synchronous separator circuit 11 separates a horizontal synchronizing signal from an input signal, the separated signal is compared with a signal from the frequency divider 8 at a frequency comparator 13 via a PLL 12 and the output is fed to the adder 5 through a switch 14 to constitute a frequency synchronous loop 20. The output signal of an asynchronous detection circuit 29 turns on the switch 14 at the asynchronous state, adds the frequency synchronous loop 20 to the phase locked loop 10 to correct frequency locking.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Field of industrial application B. Summary of the invention C. Prior art D. Problems to be solved by the invention E. Means for solving the problems (Fig. 1) F. Effect G. Description of embodiment G1 synchronous circuit (first Figure) Explanation of G2 asynchronous detection (Figures 1 and 2) Effects of the invention Industrial field of application The present invention relates to a synchronization circuit used, for example, in a playback system of a video tape recorder.

B. Summary of the Invention The present invention relates to a synchronization circuit used in a playback system of a video tape recorder, etc., and has good noise resistance by adding a frequency-locked loop only when asynchronous to a phase-locked loop based on bursts. This makes it possible to obtain a good reproduced clock signal.

C. Prior art For example, in a conventional playback synchronization circuit of a video tape recorder, the phase information of the 01 wave in a synchronization signal or a burst signal is used as a basic signal1, and a PLL is used to obtain a playback clock signal synchronized with the playback signal. was.

However, in this case, if you try to increase the frequency response of the PLL and make it follow the so-called jitter, it will be extremely susceptible to the influence of noise mixed in the basic signal, and the 87N of the reproduced clock signal will deteriorate significantly. It was supposed to happen.

D. Problems to be Solved by the Invention Conventional circuits were constructed as described above. For this reason, there is a problem in that when attempting to follow so-called jitter, the 8/N ratio of the reproduced clock signal becomes extremely poor.

E Means for Solving Problems The present invention provides a phase-locked loop (L(lI) based on a burst of an input signal, a PLL (13) based on a horizontal synchronization signal of the input signal, and an output of this PLL. A synchronous circuit characterized in that it has a frequency-locked loop with reference to , and an asynchronous detection circuit for validating the frequency-locked loop only at asynchronous points of the phase-locked loop (switch (14)). be.

F. Effect: According to this circuit, by adding a frequency-locked loop only when asynchronous to a phase-locked loop based on bursts, a good recovered clock signal with good noise resistance can be obtained.

G Example G1 Description of Synchronous Circuit In FIG. 1, a reproduced video signal from, for example, a video tape recorder is supplied to an input terminal (1).

This input signal is supplied to the burst gate (2), and the burst signal in the signal is extracted. This burst signal has a frequency of, for example, 165 fH (fH is the horizontal frequency) and has phase information that serves as a signal reference. This burst signal passes through a multiplier (3), a low-pass filter (LPF) (4), and an adder (5) to a voltage-controlled variable frequency oscillator (VC).
O) (6) K supplied: h, OV CO(6) Te oscillated clock signal of, for example, 660 fH is output to the output terminal (
7).

Furthermore, this clock signal is supplied to the 1 frequency divider (8)K to form a signal of 165fH, and this signal is sent to the multiplier (3).
is supplied to This constitutes a phase-locked loop α.

Here, the multiplier (3) is supplied with all waves (for example, 6 waves) of the burst signal extracted by the burst gate (2),
Since phase synchronization is performed on this full wave, this phase loop has a structure with a good S/N ratio. However, in this case, frequency synchronization is not accurate.

Therefore, in the figure, the signal from the input terminal (1) is supplied to the synchronization separation circuit αυ to separate the horizontal synchronization signal, and this signal is supplied to the PLL (12) to form a signal of 165fH. A signal of 165 fH from the frequency generator (8) is supplied to the frequency comparator (13), and the comparison output is supplied to the adder (5) through switch I. This constitutes a frequency-locked loop.

However, if a highly responsive PLLα2 is used here, the noise resistance characteristics deteriorate as described above.

On the other hand, if a device with a slow response speed is used and the frequency synchronization loop is operated continuously using this signal, the transient signal will become a disturbance and will instead disturb the frequency synchronization.

Therefore, in this figure, a switch (14) is provided in the frequency synchronization loop (2), and this switch α4 is turned on only when the frequency synchronization is out of synchronization. As a result, the S/N ratio is not degraded during synchronization, and a good reproduced clock signal with phase and frequency synchronization can be obtained.

G2 Explanation of asynchronous detection Furthermore, in the figure, the separated horizontal synchronization signal from the synchronization separation circuit aυ is supplied to the reproduction horizontal synchronization generation circuit 01), and as shown in the waveform diagram of FIG. 2, for example, this signal a is The load terminal trap of the psychic pulse generation circuit (c) is supplied through the inverter.

Here, the generating circuit (c) is a counter that counts, for example, 163, and the counting terminal receives 165fH from the branching device (8).
When clock signal b (see waveform diagram) is supplied, counting starts from the rising edge of the next signal after signal a, and the output during this period is set to '0', and 163 is counted. Afterwards, the output is set to "1", and a "window", k, and XC with a path width as shown in the waveform diagram is formed.

This window pulse C and the reproduction synchronization signal a are connected to a NAND circuit
This output signal is supplied to the load terminal of the counter (C) through the AND circuit (C). A clock signal S is supplied to the counting terminal of this counter (A), this counter (C) counts 165, and its carry output is supplied to an AND circuit (To) through an inverter (5).

As a result, the horizontal synchronization output synchronized with the reproduction synchronization signal a is output from the counter (c) to the output terminal (to), and when the reproduction synchronization signal a is lost due to noise etc. Interpolation of the synchronous output is performed by counting. Furthermore, by cutting off the reproducing synchronizing signal a except at desired times using the window pulse C, malfunctions due to noise or the like are prevented.

In the above waveform diagram, during normal operation shown on the upper side, the positions of signal a and signal C match, but
When the frequency synchronization is asynchronous, the positions do not match as shown below, and this allows the asynchronous detection.

That is, in the figure, the reproduction synchronization signal a from the reproduction horizontal synchronization generation circuit 21) and this phase inverted signal are transmitted to the asynchronous detection circuit -
Further, the window pulse C from the window pulse generation circuit (c) is supplied to the detection circuit (to).

Then, the level of the window pulse C at the rising and falling points of the signal a (when the inverted signal rises) is detected, and when both of these are '1', it is considered to be in a synchronous state, and even if either one is '1', the level of the window pulse C is detected. When the output signal becomes "O", an output signal is taken out as an asynchronous state.

In this way, an asynchronous state is detected, and by turning on the switch I at this time, a phase-locked loop α [K frequency-locked loop (A) is added, and frequency synchronization is corrected.

Here, by setting the pulse width of the reproduction synchronization signal to 1 clock period and the pulse width of window pulse C to 2 clock periods, not only the completely asynchronous state shown on the right side of the waveform diagram but also the state shown on the left side In this way, it is also possible to detect a mis-synchronization state of one clock cycle.

In addition, in the above circuit, the configuration other than the detection circuit used for detecting asynchrony is generally an existing circuit for interpolating missing horizontal synchronization, and a detection circuit consisting of a simple logic circuit is added. It can be easily formed using only a single circuit, and therefore the circuit scale does not increase.

H Effects of the Invention According to the present invention, a frequency-locked loop is added to the burst-based phase-locked loop only when it is asynchronous, making it possible to obtain a good recovered clock signal with good noise resistance. Became.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an example of the present invention, and FIG. 2 is a waveform diagram for explaining the same. (2) is a burst gate, 鵠 is a phase-locked loop, αυ is a synchronous separation circuit, α2 is a PLL, αhiro is a switch, ■ is a frequency-locked loop, and 翰 is an asynchronous detection circuit.

Claims (1)

[Claims] A phase-locked loop based on a burst of an input signal, a PLL based on a horizontal synchronization signal of the input signal, a frequency-locked loop based on the output of this PLL, and a phase-locked loop based on the output of the PLL. and an asynchronous detection circuit for validating the frequency-locked loop only when the frequency-locked loop is asynchronous.