JPH0828829B2 - Synchronous circuit of television receiver - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a synchronizing circuit of a television receiver in which horizontal synchronization and vertical synchronization are stabilized.

[Conventional technology]

Conventionally, the width of the window pulse of automatic frequency control (hereinafter referred to as AFC) of the horizontal synchronizing circuit of the television receiver is
For example, it was fixed as described in Japanese Patent Publication No. 61-11023.

Further, the vertical synchronizing circuit only detects the vertical synchronizing signal as described in Japanese Utility Model Publication No. 61-14229.

[Problems to be solved by the invention]

In the above-mentioned conventional technology, with respect to horizontal synchronization, in order to prevent malfunction due to the influence of noise and to reduce screen distortion during AFC free run, a narrow window pulse, and at the time of channel switching, to speed up the AFC response, There is a problem in that the pulse width of the wind pulse is fixed, although a wide wind pulse is required for each.

Further, regarding the vertical synchronization, there is a problem that the screen is disturbed only when the vertical synchronization signal is detected and when the vertical synchronization signal cannot be detected.

An object of the present invention is to provide a synchronizing circuit for a television receiver which solves such a problem and is capable of obtaining a stable synchronizing signal output.

[Means for solving problems]

To achieve the above object, the present invention relates to horizontal synchronization, a window pulse generating circuit for generating window pulses having different pulse widths, a selection circuit for switching and selecting the window pulse, and a synchronization lock detecting means. And a state determination circuit that determines the switching timing of the selection circuit and controls the selection circuit.

Further, regarding the vertical synchronization, the present invention is provided with a circuit which, when the vertical synchronization signal is missing, creates an additional vertical synchronization signal for compensating for the missing vertical synchronization signal.

[Action]

Regarding horizontal synchronization, when the state determination circuit detects that the channel switch has been pressed, the selection circuit is controlled so as to select a window pulse having a wide pulse width. When the synchronization lock detecting means detects that the horizontal synchronization is locked, the state determination circuit switches and controls the selection circuit to select a window pulse having a narrow pulse width.

For vertical synchronization, use the counter to set the horizontal synchronization frequency to 2
The double frequency is counted, and if the vertical synchronizing signal is not detected even after the stipulated time, the additional vertical synchronizing signal creating circuit causes the additional vertical synchronizing signal to be created.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a synchronizing circuit of a television receiver according to the present invention, in which 101 is a horizontal sync separation circuit, 102 is a phase detection circuit, 103 is a low pass filter, and 104 is a voltage controlled oscillator ( (Hereinafter referred to as VCO), 105 is a crystal oscillator, 106 is a frequency divider, 107 and 108 are window pulse generation circuits, 109 is a selection circuit, 110 is a state determination circuit, 111 is a channel switch, 112 is a horizontal sync pulse, and 113 is a horizontal Sync signal, 114 vertical sync separation circuit, 115 integration circuit, 116
Is a vertical synchronization detection circuit, 117 is a gate circuit, 118 is a waveform shaping circuit, 119 is a gate controller, 120 is a synthesis circuit, 121
Is a reset pulse, 122 is a counter, 123 is a gate open pulse creating circuit, 124 is a counter reset pulse creating circuit, 125 is an additional vertical synchronizing signal creating circuit, 126 is a combining circuit, 127 is a vertical synchronizing pulse, 128 is a video signal, 129 Is an AFC defeet signal and 130 is a wind pulse.

In the figure, the video signal 1
The horizontal sync signal separated from 28 enters the phase detection circuit 102. Phase detection circuit 102, low-pass filter 103, VCO 104,
The crystal unit 105 and the frequency divider 106 form a horizontal AFC circuit.

That is, if the frequency is sufficiently higher than the horizontal sync signal frequency f _H
The output signal of the VCO 104 is divided by the frequency divider 106 to obtain the frequency f _H
Horizontal sync pulse 112 is formed. This horizontal sync pulse 112 becomes the output horizontal sync pulse of this embodiment, and is also supplied to the phase detection circuit 102, where the horizontal sync separation circuit 1
The phase is compared with the horizontal sync signal output from 01. The detection output signal of the phase detection circuit 102 is processed by the low pass filter 103 and supplied to the VCO 104 as a control voltage. The control voltage controls the oscillation frequency of the VCO 104 so that the phase relationship between the horizontal sync signal supplied to the phase detection circuit 102 and the horizontal sync pulse 112 has a predetermined relationship.

Here, in order to ensure the phase detection in the phase detection circuit 102, two window pulse generation circuits for generating window pulses whose phases are synchronized with the horizontal synchronization pulse 112 from the frequency divider 106 with mutually different pulse widths. Selection circuit for selecting either 107, 108 or one of these window pulses
109 and these wind pulse generation circuits 107, 1
The window pulse 130 from the one selected by the selection circuit 109 of 08 is supplied to the phase detection circuit 102. The phase detection circuit 102 is a gate circuit that opens the pulse period of the window pulse 130 to allow the horizontal sync signal from the horizontal sync separation circuit 101 to pass through, a horizontal sync signal that has passed through this gate circuit, and a horizontal sync signal from the frequency divider 106. It has a phase comparison circuit for comparing the phase with the synchronization pulse 112.
The phase difference between the horizontal synchronizing signal within the pulse period of 130 and the horizontal synchronizing pulse 112 from the frequency divider 106 is detected. In this way, the phase detection circuit 102 is prevented from responding to unwanted pulses other than the horizontal synchronizing signal.

The selection circuit 109 is controlled by the state determination circuit 110. This state determination circuit 110 is composed of a phase detection circuit 102, a low-pass filter 103, a VCO 104 and a frequency divider 106.
The FC circuit is provided with a sync lock detecting means for detecting whether or not the horizontal sync signal from the horizontal sync separating circuit 101 is synchronously locked, and the state of the channel switch 111 pushed at the time of switching the channel and the sync lock detecting means. The state of the AFC circuit is determined by the detection result, and when the channel switch 111 is pressed, the selection circuit 109 controls to select a window pulse having a wide pulse width, and the synchronization lock detection means synchronizes the AFC circuit. When the lock state is detected, the selection circuit 109 controls to select a window pulse having a narrow pulse width.

Here, the window pulse creation circuit 107 generates a window pulse having a narrow pulse width, and the window pulse creation circuit 107
It is assumed that 108 generates a window pulse having a wide pulse width.

In this way, when the channels are switched, a wide pulse pulse is used so that the synchronization lock of the AFC circuit is performed quickly, and when the AFC circuit is in the synchronization lock state,
By using a wind pulse with a narrow pulse width,
The AFC circuit is designed to operate stably without being affected by unwanted pulses.

The vertical sync signal separated from the video signal 128 by the vertical sync separation circuit 114 is an integration circuit 115 and a vertical sync detection circuit 116.
And is extracted as a pulse waveform. Since this pulse width is shorter than three times the horizontal synchronizing signal period, the gate circuit 11
After passing 7, the waveform shaping circuit 118 shapes the pulse width to three times the horizontal synchronizing signal period. The output pulse of the waveform shaping circuit 118 is reset pulse 121 to the counter 122 that counts the pulse of frequency 2f _H from the frequency divider 106 via the synthesis circuit 120.
, And the counter 122 is set to the reset state during the pulse period. When the counter 122 is reset, as will be described later, the gate controller 119 causes the gate circuit 117 to close, and the gate circuit 117 opens shortly before the next vertical synchronization signal is supplied from the vertical synchronization detection circuit 116. .

Since the width of the pulse output from the waveform shaping circuit 118 is three times the horizontal synchronizing signal period, 190.5 μsec (63.5 μse)
c × 3). This is the reset pulse 12 of the counter 122
Since it is 1, the counter 122 starts counting (the reset is released) 190.5 μsec after the signal is output from the waveform shaping circuit 118. When the gate open pulse generation circuit 123 detects the count value of the counter 122 indicating the timing slightly before the next vertical sync signal is separated by the vertical sync separation circuit 114, it generates a gate open pulse, and the gate open pulse of this gate open pulse is generated. At the timing, the gate controller 119 opens the gate circuit 117.

When the vertical synchronizing signal comes in, the gate circuit 117 is closed through a loop of the waveform shaping circuit 118, the synthesizing circuit 120, the counter 122, the gate open pulse generating circuit 123, and the gate controller 119. If the vertical synchronizing signal does not come in even after the timing to come in, the counter reset pulse creating circuit 124 creates the reset pulse 121 and resets the counter 122. Then the gate circuit 117
Is closed.

At the same time that the counter reset pulse creating circuit 124 creates the reset pulse 121, the additional vertical synchronizing signal creating circuit 125 forcibly creates a signal in order to supplement the vertical synchronizing signal that has not been input. This signal and waveform shaping circuit 118
The signal obtained by synthesizing the output signal of 1 by the synthesizing circuit 126 is the vertical synchronizing pulse 127. When channel switch 111 is pressed,
The gate controller 119 opens the gate circuit 117 until a signal is output from the waveform shaping circuit 118.

The AFC defeet signal 129 is a signal that suppresses the operation of the phase detection circuit 102 during the vertical blanking period in order to prevent the phase detection circuit 102 from malfunctioning due to an equivalent pulse in the vertical blanking period.

FIG. 2 (a) is a circuit diagram showing an embodiment of the horizontal synchronizing signal processing section according to the present invention shown in the upper part of FIG.
The same reference numerals as those in FIG. 1 have the same functions, and 201 is a NOR circuit, 20
2 is an AND circuit, 203 is an OR circuit, 204 is a NOR circuit, 205 is an AND circuit, 206 is an OR circuit, 207 is a counter, 208 is an AND circuit, 209
Is a flip-flop (hereinafter referred to as FF), 210 is an inverter, and 211 is a pull-up resistor.

FIG. 2B is a timing chart of FIG.

In FIG. 2 (a), the counter 106 constitutes the frequency divider 106 of FIG. 1, the NOR circuit 201, the AND circuit 202, and the OR circuit 203 constitute the window pulse generation circuit 107 of FIG. 1, and the NOR circuit.
204, AND circuit 205, and OR circuit 206 constitute the window pulse generation circuit 108 of FIG. 1, and the counter 207 and AND circuit 208 constitute the above-mentioned synchronous lock detecting means, and this synchronous lock detecting means, FF209 and inverter. 210 is the state determination circuit of FIG.
Make up 110.

The operation of the horizontal synchronizing signal processing section will be described with reference to FIGS. 2 (a) and 2 (b).

The inputs A and B of the selection circuit 109 are connected to the output of the OR circuit 203, O
The output of the R circuit 206 is input. In the state where the horizontal synchronization is already locked, the output Q of the FF 209 is “L”, and the input A is selected as the window pulse 130 in the selection circuit 109. Channel switch 111 in this state
When is pressed, the set input of FF209 becomes "H" and its output Q becomes "H". Then, the selection circuit 109 selects the input B as the window pulse 130 this time. Input B
In this case, the width of the wind pulse is wider, so that the horizontal sync pull-in becomes faster.

Then, when the horizontal sync signal from the horizontal sync separation circuit 101 comes into the pulse period of this window pulse, the horizontal sync signal passes through the gate circuit in the phase detection circuit 102 and then the horizontal sync signal from the counter 106. Sync pulse 1
It is used for phase comparison with 12 and horizontal sync signal 113
Is supplied to the counter 207 and is counted. This state continues, and finally the AFC circuit composed of the phase detection circuit 102, the low-pass filter 103, the VCO 104 and the counter as the frequency divider 106 is synchronously locked to the horizontal sync signal supplied from the horizontal sync separation circuit 101. But this is
The counter 207 is detected by counting the horizontal synchronizing signal 113 by a predetermined number (here, 50 times).

Therefore, when the counter 207 counts this predetermined number,
Assuming that the above AFC circuit is in the synchronous lock state, AND circuit
The “H” reset pulse is output from 208. This reset pulse resets the FF 209, its Q output becomes "L", and the selection circuit 109 selects the window pulse of the input A.

When the channel switch 111 is pressed, the counter 207 is reset.

FIG. 3A is a block diagram showing a specific circuit configuration of the vertical synchronizing signal processing unit according to the present invention shown in the lower portion of FIG. 1, and is the same as FIG. 1 and FIG. 2A. Reference numerals have the same function, 301 and 302 are resistors, 303 is an operational amplifier (hereinafter,
OP), 304 is a pull-up resistor, 305 is an AND circuit, 306
Is FF, 307 is counter, 308 is AND circuit, 309 is FF, 310 is A
The ND circuit, 311 and 312 are mono-multi (hereinafter referred to as MM).

FIG. 3B is a timing chart of FIG.

In FIG. 3A, the resistors 301 and 302 and the OP 303 constitute the vertical synchronization detection circuit 116 of FIG. 1, the gate circuit 117 is constituted by a 3-state inverter, and the waveform shaping circuit 118 is constituted by monomulti. FF306 and AND circuit 305
Constitutes the gate controller 119 of FIG.
20 is composed of an OR circuit. The counter 307 constitutes the counter 122 of FIG. 1, the AND circuit 308 and FF 309 are the gate open pulse generating circuit 123 of FIG. 1, and the AND circuit 310 and the monomulti 311 are the counter reset pulse generating circuit of FIG. 124 respectively. The mono-multi 312 constitutes the additional vertical synchronizing signal generating circuit 125 of FIG.
It is composed of an OR circuit.

The operation of the vertical synchronizing signal processing section will be described with reference to FIGS. 3 (a) and 3 (b).

The gate circuit 117, when the output of the AND circuit 305 is “L”,
It is open and operates as an inverter, and AND circuit 305
When the output of is “H”, it becomes a high impedance state and closes.

Now, the output of the AND circuit 305 is "L", and the gate circuit
When the output of OP303 becomes “H” when 117 is open (that is, when the vertical synchronizing signal is detected), the gate circuit 11
The output of 7 becomes "L" (when the output of OP303 becomes "H", the output of the gate circuit (3 state inverter) 117 becomes "L"). Then, the output of the waveform shaping circuit (MM) 118 becomes "H", but the pulse width is set to 190.5 μsec by the external capacitor C and the resistor R. MM11
When the output Q of 8 becomes "H", the output of the synthesis circuit (OR circuit) 120 becomes "H". Then, the counter 307 is reset, all the outputs of this counter 307 become "L", and the AND circuit
Since the output of 308 becomes "L", the set input of FF309 becomes "L".
Also, since the output of “H” of the synthesis circuit 120 becomes the reset input of this FF309, the set input of FF309 is “L”,
The reset input becomes “H” and the FF309 output becomes “H”.

Further, since the set input of the FF 309 becomes "H" by the output of "H" of the synthesizing circuit 120, its output Q becomes "H". AN
Since both inputs of D circuit 305 become “H”, AND circuit 305
Output becomes "H", and the gate circuit 117 is closed (high impedance).

Since the output of the gate circuit 117 is pulled up by the pull-up resistor 304, it becomes “H” at the same time when it is closed.

As described above, when the gate circuit 117 is in the open state, the vertical synchronizing signal is detected by the OP 303, its output rises, the output of the gate circuit 117 falls accordingly, and the output of the waveform shaping circuit 118 becomes “ When it becomes H ", the output of the AND circuit 305 immediately becomes" H "and the gate circuit 117 is closed. Therefore, in the gate circuit 117, only the rising edge portion of the detected vertical synchronizing signal passes.

190.5 μse after the output of the waveform shaping circuit 118 goes to “H”
It becomes “L” after c. Then, the counter 307 is released from the reset state and starts counting with the output 2f _H (f _H is a horizontal synchronizing frequency) of the frequency divider (counter) 106 as a clock.
When 516 2f _H ((63.5 μsec / 2) × 516 = 16383 μsec) are counted, the output of the AND circuit 308 becomes “H” and the output of the FF 309 becomes “L”. Since one of the inputs of the AND circuit 305 becomes “L”, the output also becomes “L”, the gate circuit 117 is opened, and the input of the vertical synchronizing signal is waited.

When the vertical sync signal is input, the output of MM118 is “H”,
The output of the synthesis circuit 120 is “H”, the counter 307 is reset, its output is “L”, the output of the AND circuit 308 is “L”, FF309
Becomes "H", the output of the AND circuit 305 becomes "H", the gate circuit 117 is closed, and the same loop is followed.

Even if the counter 307 counts 521 pulses with a frequency of 2f _{H and} the vertical synchronizing signal does not come in, the output of the AND circuit 310 is “H”, the output Q of the MM311 is “H”, the output of the synthesis circuit 120. Becomes "H" and the gate circuit 117 is closed. The pulse width of the output of the MM311 is set to 127 μsec (63.5 μsec × 2).

Further, when the output of the AND circuit 310 becomes "H", the output of the MM312 also becomes "H". This output is set to have a pulse width of 190.5 μsec because it is used as a vertical synchronization signal that is forcibly added when the vertical synchronization signal cannot be detected. The vertical synchronizing signal forcibly added and the detected vertical synchronizing signal are combined by the combining circuit 126, and the vertical synchronizing pulse 127
And

According to the present invention, with respect to horizontal synchronization, once synchronization is locked, the width of the window pulse can be narrowed, malfunctions due to noise can be prevented, and distortion of the screen during free run can be reduced. , It is possible to widen the width of the wind pulse and speed up the synchronization pull-in. Regarding the vertical synchronization, even if the synchronization signal cannot be detected, since the vertical synchronization signal created in the receiver is added to almost the same position, the disturbance of the vertical synchronization can be eliminated.
Further, by using the gate circuit 117, malfunction due to noise can be prevented.

〔The invention's effect〕

As described above, according to the present invention, since horizontal and vertical synchronization can be stabilized, it is possible to obtain a screen that is not disturbed even when the reception state changes such as an in-vehicle television receiver. Except for the drawbacks, it is possible to provide a television receiver synchronization circuit with excellent functions.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a synchronizing circuit of a television receiver according to the present invention, and FIG. 2 (a) is a circuit diagram showing an embodiment of a horizontal synchronization processing unit of FIG. 1, FIG. 2B is a timing chart of FIG. 2A, FIG. 3A is a circuit diagram showing an embodiment of the vertical synchronization processing unit of FIG. 1, and FIG. 3B is FIG. 3A. ) Is a timing chart. 107,108 …… Wind pulse creation circuit, 109 …… Selection circuit, 110 …… Status judgment circuit, 117 …… Gate circuit, 108…
… Waveform shaping circuit, 119 …… Gate controller, 122 ……
Counter, 123 ... Gate open pulse generation circuit, 124
…… Counter reset pulse creation circuit, 125 …… Additional vertical synchronization signal creation circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Atsushi Sato 1410 Inada, Katsuta City, Ibaraki Pref., Hitachi Ltd.

Claims (2)

[Claims] 1. A horizontal synchronization processing unit for generating a horizontal synchronization pulse synchronized with a horizontal synchronization signal of a received video signal, and a vertical synchronization processing unit for generating a vertical synchronization pulse synchronized with a vertical synchronization signal of the video signal. And a horizontal synchronization separation circuit for separating the horizontal synchronization signal from the video signal, a voltage controlled oscillator, and an output of the voltage controlled oscillator. A frequency divider that divides and forms the horizontal sync pulse having the same frequency as the horizontal sync signal; a window pulse generation circuit that forms a plurality of window pulses that are phase-synchronized with the horizontal sync pulse and have different pulse widths; A selection circuit for selecting any one of the plurality of window pulses, and detecting and detecting the horizontal synchronization signal from the horizontal synchronization separation circuit by the window pulse from the selection circuit. A phase detection circuit for detecting the phase relationship between the output horizontal synchronization signal and the horizontal synchronization pulse from the frequency divider, and a detection output signal of the phase detection circuit for processing a control signal of the voltage controlled oscillator. An automatic frequency control circuit including a low-pass filter for generating, a channel selection instructing means for instructing channel selection, the voltage controlled oscillator, the frequency divider, the phase detection circuit, and the low-pass filter converts the horizontal synchronization signal into a horizontal synchronization signal. A state determination is provided that includes a synchronization lock detection unit that detects that synchronization has been locked, determines the state of the synchronization lock detection unit and the state of the channel selection instruction unit, and controls the selection circuit according to the determination result. And a circuit for selecting a channel from the window pulse having a wide pulse width when the channel selection is instructed by the channel selection instructing means. Select and synchronous lock detecting means detects the synchronization lock, the synchronization circuit of the television receiver, characterized in that the pulse width of the window pulse to select a narrow window pulse. 2. A synchronizing circuit for a television receiver according to claim 1, wherein the vertical synchronizing processing section is: a vertical synchronizing separating circuit for separating the vertical synchronizing signal from the video signal; A gate circuit that passes the vertical synchronization signal separated by the vertical synchronization separation circuit, and the gate circuit is closed at the timing of the vertical synchronization signal that has passed through the gate circuit. First opening the gate circuit at a timing immediately before a vertical synchronizing signal is supplied to the circuit;
And the control circuit for closing the gate circuit when the vertical synchronization signal is not supplied from the vertical synchronization separation circuit to the gate circuit even if the open state of the gate circuit has passed for a predetermined period. Synchronizing circuit for a television receiver, comprising: a second control means for generating the signal; and a synthesizing circuit that uses the vertical synchronizing signal that has passed through the gate circuit and the additional vertical synchronizing signal as the vertical synchronizing pulse. .