JP3212658B2 - Pulse signal generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse signal generating circuit used for a color signal processing circuit of a video tape recorder (VTR), for example.

[0002]

2. Description of the Related Art At present, VHS type VTRs are predominant, but from the viewpoint of miniaturization, 8 mm type VTRs are also becoming popular. Comparing both types of color signal processing methods, the methods are very similar, so if both types of color signal processing circuits are configured with one IC and can be switched and used by both types, Cost reduction can be expected due to increased mass production effect. For that, the common IC is 8m
There is no point in increasing the size of the circuit for switching by the m / VHS method.

One of the differences between the VHS system and the 8 mm system is that the low frequency conversion frequency is different. The low-band converted frequency signal after 1 / N dividing a signal of a frequency f ₀ output from the voltage-variable oscillator (VCO), it is created by locking it to the horizontal scanning frequency f _H.
Therefore, the oscillation frequency of the VCO is set to f ₀ (f ₀ = N
f _H ), in a VTR employing the NTSC mode VHS method, N = 320 and f ₀ = about 5 MHz (the same applies to PAL). On the other hand, VT adopting 8mm method
In R, f ₀ = about 6 MHz (the same applies to PAL) when N = 378, and there is a difference of nearly 20% in frequency between both methods. With the proviso that f _H = 15.734KHz.
This is a serious problem for the pulse generation circuit formed on the common IC that operates using the output signal of the VCO as a clock. In this case, the pulse generation circuit cannot be used commonly for both types without switching the circuit configuration. Will be.

FIG. 6 is a block diagram showing an example of a conventional color signal processing circuit including the above-mentioned pulse signal generating circuit.
However, in this circuit, the circuit that operates as a 1 / N frequency divider during recording operates as a counter of a frequency discriminator during reproduction. A composite synchronizing signal 50 is input to the pulse generating circuit 1, and an inverted signal of the composite synchronizing signal 50 by the inverter 14 is supplied to the clock terminal CK of the D flip-flop 11.
Is input to The mask pulse 60 is input from the counter 12 to the data terminal D of the D flip-flop 11. The reset terminal R of the D flip-flop 11
, A delay signal of the pulse 100 output from the output terminal Q by the delay circuit 13 is input. The clock terminal CK of the counter 12 has a voltage-controlled oscillator (V
CO), a clock 70 having a frequency f ₀ is input, and the counter 12 counts this signal. As a result, the output terminal Q of the D flip-flop 11
A reset pulse 100 as shown in FIG.
The reset pulse 100 is input to the reset terminal of the counter 12 and to the clock terminal CK of the T flip-flop 2-1.

[0005] From the output terminal Q of the T flip-flop 2-1, a square-wave pulse 201 as shown in FIG.
Is output to the clock terminal CK of the T flip-flop 2-2 and to the gates 3 and 4. From the output terminal Q of the T flip-flop 2-2, a square pulse 2 as shown in FIG.
02 is output, and this pulse 202 is input to the clock terminal CK of the T flip-flop 2-3 and also to the gate 3 and the gate 4. T flip-flop 2-
7 outputs a square-wave pulse as shown in FIG. 7D, and this pulse is input to the gate 4 and also to the AND gate 5. Gate circuit 3,
Reference numeral 4 denotes an AND gate, and each input with a circle means that a signal supplied to the input is input after its signal is logically inverted. As a result, a reset signal 300 as shown in FIG.
Is output to the reset terminal R of the counter 6. On the other hand, a gate control signal 400 as shown in FIG. 7F is output from the gate 4, and the gate control signal 400 is input to the AND gates 7 and 8. On the other hand, the other terminal of the AND gate 5 receives the clock 70 of the frequency f ₀ output from the above-mentioned VCO (not shown), and the AND condition with the pulse 203 output from the T flip-flop 2-3 is taken. , And the result is input to the clock terminal CK of the counter 6. As a result, the ID signal 501 shown in FIG.
The ID signal 502 shown in (H) is output and the ID signal 5
01 is input to the AND gate 7, and the ID signal 502 is input to the AND gate 8.

Accordingly, the T flip-flops 2-1 to 2-
When the output pulses 201 to 203 of (3) are (1, 0, 0), the gate control signal 400 is output from the gate 4 to the AND circuits 7 and 8. Thereby, the AND gates 7, 8
Opens. The pulses 201 to 203 are (0, 1,.
At the time of 0), the reset pulse 300 is output from the gate 3 to the counter 6, and the counter 6 is reset. After the counter 6 is reset, the T flip-flop 2-3
Output pulse 203 becomes "1", and the AND gate 5 is opened for a period of 4H (H is a horizontal period, the same applies hereinafter). This 4
During the H period, the clock 70 output from the VCO becomes the clock input of the counter 6, and the counter 6 counts this clock. During this counting period, the counter 6
ID signals 501 and 502 as shown in (G) and (H) are output to AND gates 7 and 8. After the count period of the count 6, the pulse 203 shown in FIG. 7D output from the T flip-flop 2-3 becomes low level. Therefore, the AND gate 5 is closed, the clock 70 is not input to the counter 6, and the counter 6 enters the hold state. Accordingly, the counter 6 outputs the above-described ID signals 501 and 502 again during the next counting period.

When the frequency f _{0 of the} clock 70 is in a steady state, the counter 6 outputs the ID signals 501 and 502 when the AND gates 7 and 8 are closed. It is "0".
However, when the frequency f _{0 of the} clock 70 increases,
After the counter 6 counts for the 4H period, the ID signal 501 remains "0", but the ID signal 502 becomes "1" as shown by the broken line in FIG.
A signal 502 is output to discriminate that the clock frequency has increased. Conversely, when the frequency f ₀ of the clock 70 decreases, after the counter 6 counts for the 4H period, ID
The signal 501 is "1" as shown by the dashed line in FIG.
Since the ID signal 502 remains "0", the ID signal 501 is output from the AND gate 7 to discriminate that the clock frequency has decreased. Such circuit in FIG. 6 is used for its construction it is relatively simple, since the frequency f ₀ of the VCO output is a clock 70, as described above differs greatly VHS type and 8mm system, the pulse generator The circuit 1 cannot be used without switching according to the method. Therefore, a circuit for switching the circuit configuration of the pulse generation circuit 1 in correspondence with two types of clocks is required, and there is a problem that the circuit scale is increased and the integration into an IC is hindered. Further, it is conceivable to divide the frequency of the clock 70 by the counter 6 so that the pulse generation circuit 1 can be commonly used in each system. However, as described above, the stop period of the counter 6 is 4H, which is not possible. is there. Therefore, when the pulse generation circuit 1 is shared by the respective methods, a dedicated counter for dividing the frequency of the clock 70 at the time of reproduction must be provided, which is also not preferable because the circuit scale becomes large.

[0008]

In the above-described conventional color signal processing circuit, the recording / reproducing circuit operates as a 1 / N frequency divider during recording.
At the time of reproduction, the counter operated as a frequency discriminator is 4
Since the H period is also stopped, this counter is used for the VHS system and 8
There was a drawback that it could not be used in common for both types of mm system. Also, since clocks of different frequencies are supplied to the pulse generation circuit in the VHS system and the 8 mm system, a circuit for switching the circuit configuration of the pulse generation circuit corresponding to the two types of clocks is required. There was a drawback that the scale was increased and it was not suitable for IC.

Therefore, the present invention is to eliminate the above-mentioned disadvantages, and to improve the recording time in both the 8 mm system and the VHS system.
A frequency divider which operates as a / N frequency divider and can be used by switching between both types as a frequency discriminator at the time of reproduction is provided, and a pulse signal which can be commonly used by both types is obtained from this frequency divider. It is an object to provide a pulse signal generation circuit.

[0010]

A pulse signal generating circuit according to the present invention is supplied with an input pulse signal having one of a first frequency and a second frequency different from the first frequency, and controls the pulse signal. A gate circuit that operates to output the input pulse to its output terminal or to block the output based on the signal, a frequency divider that divides the pulse signal passed through the gate circuit by 1 / n, A pulse extraction signal generation circuit for outputting an extraction signal for controlling the operation of the gate circuit so as to block and extract the k input pulse signals based on the frequency division output of the frequency divider so as to block the passage of the input pulse signals at every frequency division cycle; When the frequency of the input pulse signal is a first frequency,
The sampling signal is supplied to the gate circuit as the control signal, and control is performed so as to obtain a frequency-divided output of 1 / (n + k) as the output of the frequency divider. When the frequency of the input pulse signal is the second frequency, Control means for supplying a signal for passing the input pulse as the control signal to the gate circuit, and controlling so as to obtain a 1 / n frequency-divided output as an output of the frequency divider; and clocking the output of the gate circuit. Output means for outputting to the utilization circuit as a signal.

[0011]

In the pulse signal generating circuit of the present invention, the input pulse signal has at least two kinds of frequencies, and the gate circuit guides the input pulse signal to the frequency divider. The frequency divider divides the output of the gate circuit by 1 / n. The pulse extraction signal generation circuit generates a pulse extraction signal for extracting k pulses from the input signal every one division cycle of the frequency divider by closing the gate circuit based on the frequency division output of the frequency divider. The control means closes the gate circuit with the pulse extraction signal, extracts k pulses from the input signal, and supplies the pulse to the frequency divider to set the frequency division ratio of the frequency divider to 1 / (n + k). Or, the gate is opened irrespective of the pulse extraction signal, and the division ratio of the frequency divider is set to 1 / n. The output means outputs the output of the gate circuit to a utilization circuit as a clock. Even if the frequency of the input pulse signal output from the variable frequency oscillator is changed by the VHS method and the 8 mm method, the dividing ratio determined by the pulse sampling circuit composed of the pulse sampling signal generation circuit and the gate circuit and the frequency divider Can be set so that the frequency of the signal output from the gate circuit does not change so much on average.By using this signal as a clock, the circuit configuration of the pulse generation circuit that generates various pulses can be changed. This eliminates the need to switch between the VHS system and the 8 mm system.

[0012]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a color signal processing circuit including a pulse signal generating circuit at the time of recording according to the present invention. 1 is a pulse generation circuit that generates various pulses based on a clock 75 output from the pulse extraction circuit 21;
A pulse extracting circuit 21 extracts a pulse from the input clock 70 at a predetermined interval to generate a clock 75 and outputs the clock 75. The pulse extracting circuit 21 includes a mask pulse generating circuit 211, an OR gate 212, and an AND gate 213. 22-1
Is a frequency divider that divides the input clock by 1 / n, 22-2 is a frequency divider that divides the input clock by 1 / m, and 23 is a sample that samples and holds the frequency-divided signal of the frequency divider 22-2. A hold circuit, 24 is a sampling control circuit for generating a pulse sampling control signal 40 of the pulse sampling circuit 21, 25 is a frequency divider for dividing the input reference pulse 250 by 1 / k, 26 is a reference pulse and 1/1 of this reference pulse. This is an AND gate that takes an AND condition with the k-divided signal. The frequency dividers 22-1 and 22-2
Form a 1 / N frequency divider, the frequency divider 22
The output of -2 is a signal obtained by dividing the clock 75 by 1 / N.

Next, the general operation of this embodiment will be described. At the time of recording, when the control signal 40 output from the sampling control circuit 24 is “0” (that is, corresponding to the 8 mm system), the pulse sampling circuit 21 outputs a frequency f ₀ generated from a VCO (not shown).
Extract k pulses from the clock of
5 is output to the pulse generation circuit 1 and the frequency divider 22-1. Therefore, in this case, the pulse sampling circuit 21 operates equivalently as a 1 / (m + k) frequency divider. However, when the control signal 40 output from the sampling control circuit 24 is "1" (that is, for the VHS system), the pulse sampling is not performed by the pulse sampling circuit 21, so that the clock 70 passes through this circuit 21. Is output as the clock 75 as it is.

The pulse sampling control of the pulse sampling circuit 21 is performed by a sampling control circuit 24 based on a feedback signal from a frequency divider 22-2. The output frequency of the frequency divider 22-2, that is, the output frequency of the frequency divider 22-2 is set by the setting of the sampling control. , 1 / N can be changed. On the other hand, period 1H
Reference pulse 250 (frequency f _H) is turned 1 / k frequency-divided by kH period of the signal by that will be input to the frequency divider 25 is input to the AND gate 26. The reference pulse 250 is directly input to the other input of the AND gate 26. The AND gate 26 takes the AND condition of the two input signals, inputs the resulting signal 350 to the reset terminals of the frequency dividers 22-1 and 22-2, and inputs the signal 350 to the sample / hold circuit 23 as a sample / hold signal. input. Therefore, if the pulse width of the signal 350 is reduced, the sample and hold circuit 23 holds the number of pulses in the kH period of the output signal of the frequency divider 22-2 to perform frequency discrimination. In addition, at this time, the 1 / N frequency divider composed of the frequency dividers 22-1 and 22-2 hardly stops, so that the clock 75 output from the pulse extracting circuit 21 Can be used.

FIG. 2 is a circuit diagram showing a detailed example of the pulse sampling circuit 21 shown in FIG. 1 and a frequency divider 22-1 at the subsequent stage. When handling signals in the NTSC mode, the above N = 320 (5 × 2 ⁶ ) in the VHS system, and the sampling control signal 4
0 is set to "1". At this time, the clock 70 and passes through the AND gate 213 of the pulse sampling circuit 21, are supplied to the pulse generating circuit 1, a clock period T ₁ of the at this time _{T 1 = 1 / 320f H =} 0.199μ sec Becomes Next, in the 8 mm system, since N = 378 (6 × 2 ⁶ −6), most of the sampling control signal 40 is “0” and 1
H is set to be "1" only six times.

[0016]

[Outside 1]

From the output terminal Q of the D flip-flop 211A, a signal 214 as shown in FIG. 3 (F) is output to the gate 211B. The other input of the gate 211B receives the output signal of the gate 22-14. Thus, a mask pulse 215 as shown in FIG. 3G is output from the gate 211B to the OR gate 212.
The above-described sampling control signal 40 is input to the other input of the OR gate 212. Here, the initial values of the signals 221 , 222 , and 223 output from the output terminals Q of the D flip-flops 22-11 to 22-13 are set to (0,
0, 0). From this, the clock 75 is frequency-divided by 1/5 by the D flip-flops 22-11 to 22-13, and the output signal 214 of the D flip-flop 212A is changed to "1" from the fourth clock shown in FIG. Until “1”, the mask pulse 215 output from the gate 211B becomes “0” as shown in FIG. Therefore, the fifth clock of the clock 70 shown in FIG. 3A is extracted as shown in FIG.

Accordingly, the D flip-flops 22-11 to 22-11
The output signal of the 1/5 frequency divider 22-13 is a signal having one cycle of the input clock 70, and the pulse output from the AND gate 213 as shown in FIG. Most of the clocks 75 after the sampling are in the state of toothlessness every 5 clocks, and the average period T ₂ is T
₂ = 6T ₀ /5=0.202 μs. This value is VH
Since the clock period is almost equal to that of the S system, the pulse generating circuit 1 shown in FIG.
Eliminates the need to specifically switch the circuit configuration between the VHS system and the 8 mm system. However, the above T ₀ = 1 / 378f _H
It is.

FIG. 4 is a block diagram showing a detailed example of the pulse signal generating circuit of the present invention. Pulse generation circuit 1 of this example
Is the same as the circuit shown in FIG. 6, except that a clock 75 generated by the pulse extracting circuit 21 is input as a clock of the counter 12. The reset pulse 100 as shown in FIG. 5A output from the pulse generation circuit 1 is input to the clock terminal CK of the T-flop 2-1 and also to the AND gate 9. A signal 201 as shown in FIG. 5B is output from the output terminal Q of the T flip-flop 2-2. This signal is input to the clock terminal CK of the T flip-flop 2-2. Input to the other input. A signal 202 as shown in FIG. 5C is output from the output terminal Q of the T flip-flop 2-2, and is input to the other input of the AND gate 9. As a result, a reset pulse 350 as shown in FIG. 5D is output from the AND gate 9, and the reset pulse 350 is reduced to 1/5.
Reset terminal of frequency divider 22-1 and 1/64 frequency divider 22
-2, and is also input to clock terminals CK of D flip-flops 27 and 28. Here, the reset pulse 100 is a T flip-flop 2-
Since the frequency is divided by 1/4 at 1, 2-2, the AND gate 9
The reset pulse 350 output from FIG.
As shown in FIG. 7, the pulse becomes a narrow pulse having a width of 4H.

Clock terminal CK of 1/5 frequency divider 22-1
Is supplied with a clock 75 output from the pulse extracting circuit 21. This clock 75 is frequency-divided by 1/5 and
The signal is input to the clock terminal CK of the / 64 frequency divider 22-2 and further frequency-divided by 1/64. As a result, the ID shown in FIG.
A signal 501 and an ID signal 502 shown in FIG. 5F are generated and input to the data terminals D of the D flip-flops 27 and 28, respectively. Therefore, D flip-flop 2
7 and 28 hold the ID signal 501 and the ID signal 502 of the frequency divider 22-2 at the cycle of the reset pulse 350 to perform frequency discrimination.

According to the present embodiment, the clock 75 output from the pulse extracting circuit 21 can be used as a reference for generating the clock 75 even if the frequency division ratio of the frequency divider connected to the subsequent stage changes. Even if the frequency of the clock 70 changes,
Since the period can be set so that it does not change much on average, the clock 75 is used as an input to the pulse generation circuit 1 without switching the circuit configuration of the pulse generation circuit 1. Can be used in common. As a result, it is not necessary to add a switching circuit required for switching the circuit configuration of the pulse generation circuit 1, and accordingly, the circuit scale can be reduced, and the circuit can be made suitable for IC.

[0022]

As described above, according to the pulse signal generating circuit of the present invention, both the 8 mm system and the VHS system operate as a 1 / N frequency divider at the time of recording, and at the time of reproduction, both operate as a frequency discriminator. It is possible to provide a frequency divider that can be switched and used in common, and to obtain a pulse signal that can be commonly used in both types from this frequency divider.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a color signal processing circuit including a pulse signal generation circuit according to the present invention.

FIG. 2 is a circuit diagram showing a detailed example of a pulse sampling circuit and a 1 / n frequency divider shown in FIG. 1;

FIG. 3 is a time chart for explaining the operation of the circuit shown in FIG. 2;

FIG. 4 is a circuit diagram showing a detailed example of a pulse signal generation circuit of the present invention.

FIG. 5 is a time chart for explaining the operation of the circuit shown in FIG. 4;

FIG. 6 is a circuit diagram illustrating an example of a color signal processing circuit including a conventional pulse signal generation circuit.

FIG. 7 is a time chart for explaining the operation of the circuit shown in FIG. 6;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Pulse generation circuit 2-1 to 2-2 ... T flip-flop 9, 26 ... And gate 21 ... Pulse sampling circuit 22-1, 22-2 ... Frequency divider 23 ... Sample hold circuit 24 ... Sampling control circuit 27 28 ...
D flip-flop

Claims (2)

(57) [Claims] An input pulse signal having one of a first frequency and a second frequency different from the first frequency is supplied, and the input pulse is output to an output terminal thereof based on a control signal. A gate circuit that operates to block or block the output, a frequency divider that divides the pulse signal that has passed through the gate circuit by 1 / n, and the input pulse signal based on the divided output of the frequency divider. A pulse extraction signal generation circuit for outputting an extraction signal for controlling the operation of the gate circuit so as to block k signals and to extract the k signals at each frequency division cycle, and wherein the frequency of the input pulse signal is a first frequency At this time, the sampling signal is supplied to the gate circuit as the control signal, and control is performed such that a frequency-divided output of 1 / (n + k) is obtained as the output of the frequency divider. frequency Control means for supplying a signal for passing the input pulse as the control signal to the gate circuit, and controlling so as to obtain a 1 / n frequency-divided output as an output of the frequency divider; and an output of the gate circuit. Output means for outputting a clock signal as a clock signal to a utilization circuit. 2. An input pulse signal having one of a first frequency and a second frequency different from the first frequency is supplied, and the input pulse is output to an output terminal thereof based on a control signal. A gate circuit that operates to block or block the output; a first divider that divides the pulse signal passing through the gate circuit by 1 / n and outputs the divided signal; A second frequency divider that divides an output pulse by 1 / m and derives the output pulse to an output terminal; and a second frequency divider that divides the input pulse signal based on a frequency division output of the first frequency divider. A pulse extraction signal generation circuit for outputting an extraction signal for controlling the operation of the gate circuit so as to block and extract k signals per 1 division period, and the control according to a frequency of the input pulse signal Supply the sampling signal to the gate circuit as a signal A 1 / (n + k) divided output is obtained as the output of the first frequency divider, or a signal for passing the input pulse is supplied to the gate circuit as the control signal, and the output of the first frequency divider is output. And the switching selection operation is stopped based on the frequency division output of the second frequency divider, and either one of them is stopped regardless of the frequency of the input pulse signal. A pulse signal generation circuit comprising: control means for controlling a divided output to be obtained; and output means for outputting an output of the gate circuit to a utilization circuit as a clock signal.